Memory system
AssigneeToshiba Memory Corporation
InventorTakayuki Takano
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory chip, a queue block and a memory controller. The queue block is configured to store a command to be transmitted to the memory chip. The queue block includes a first queue and a plurality of second queues each corresponding to a plane of the memory chip. The memory controller is configured to determine whether or not a first command enqueued in the first queue is a first read command. The first read command is a command for executing read operation in the planes asynchronously. When the first command is the first read command, the memory controller transfers the first command to one of the second queues corresponding to a plane in which the first command is to be executed. The memory controller selects the first queue or the second queues as a source of a command to be transferred to the memory chip.
Claims16
A memory system, comprising:
- a memory chip including a plurality of planes;
- a queue block configured to store a command to be transmitted to the memory chip,
- the queue block including a first queue and a plurality of second queues, the second queues respectively corresponding to the planes of the memory chip;
- and
- a memory controller configured to:
- determine whether or not a first command enqueued in the first queue is a first read command, the first read command being a command for executing a read operation in the planes asynchronously;
- when determining that the first command is the first read command, transfer the first command to one of the second queues corresponding to a plane in which the first command is to be executed;
- when determining that the first command is not the first read command, refrain from transferring the first command from the first queue so that the first command remains in the first queue;
- and
- select the first queue or the second queues as a command source to be transferred to the memory chip.
A method of controlling a memory system,
- the memory system including:
- a memory chip including a plurality of planes;
- and
- a queue block configured to store a command to be transmitted to the memory chip,
- the queue block including a first queue and a plurality of second queues, the second queues respectively corresponding to the planes of the memory chip;
- the method comprising:
- determining whether or not a first command enqueued in the first queue is a first read command, the first read command being a command for executing a read operation in the planes asynchronously;
- transferring, when determining that the first command is the first read command, the first command to one of the second queues corresponding to a plane in which the first command is to be executed;
- refraining, when determining that the first command is not the first read command, from transferring the first command from the first queue so that the first command remains in the first queue;
- and
- selecting the first queue or the second queues as a command source to be transferred to the memory chip.
Dependencies are inferred from the claim text.