Flash memory polling
AssigneeWestern Digital Technologies, Inc.
InventorsChao Sun, Xinde Hu, Dejan Vucinic
Life of this patent
Estimating the term…
Abstract
A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.
Claims23
A Data Storage Device (DSD), comprising:
- a flash memory for storing data;
- and
- a controller configured to:
- group portions of the flash memory into a plurality of logical groups based at least in part on a number of Program/Erase (P/E) cycles;
- monitor command performance latency for each logical group of the plurality of logical groups, wherein the command performance latency indicates time from command issuance to command completion;
- and
- based on the monitored command performance latency for each logical group, set at least one polling time for each respective logical group of the plurality of logical groups, wherein the at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.
A method for operating a Data Storage Device (DSD) including a flash memory for storing data, the method comprising:
- grouping portions of the flash memory into a plurality of logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions in the flash memory;
- monitoring command performance latency for each logical group of the plurality of logical groups, wherein the command performance latency indicates time from command issuance to command completion;
- and
- based on the monitored command performance latency for each logical group, setting at least one polling time for each respective logical group of the plurality of logical groups, wherein the at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command;
- and
- wherein the method is performed by a controller of the DSD.
A non-transitory computer readable medium storing computer-executable instructions, wherein when the computer-executable instructions are executed by a controller of a Data Storage Device (DSD) including a flash memory, the computer-executable instructions cause the controller to:
- group portions of the flash memory into a plurality of logical groups based at least in part on a number of Program/Erase (P/E) cycles;
- monitor command performance latency for each logical group of the plurality of logical groups, wherein the command performance latency indicates time from command issuance to command completion;
- and
- based on the monitored command performance latency for each logical group, set at least one polling time for each respective logical group of the plurality of logical groups, wherein the at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.
A Data Storage Device (DSD), comprising:
- a flash memory for storing data;
- and
- a controller configured to:
- group portions of the flash memory into a plurality of logical groups based at least in part on a number of Program/Erase (P/E) cycles;
- monitor command performance latency for each logical group of the plurality of logical groups;
- based on the monitored command performance latency for each logical group, set at least one polling time for each respective logical group of the plurality of logical groups, wherein the at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command;
- based on updated numbers of P/E cycles for the portions of the flash memory, perform at least one of adding a new logical group to the plurality of logical groups and regrouping one or more portions of the flash memory into a different logical group of the plurality of logical groups;
- in response to the addition of a new logical group to the plurality of logical groups, monitor command performance latency for each logical group of the plurality of logical groups for a predetermined number of commands in each respective logical group;
- and
- based on the monitored command performance latency for each logical group for the predetermined number of commands, set one or more polling times for each respective logical group.
A Data Storage Device (DSD), comprising:
- a flash memory for storing data;
- and
- a controller configured to:
- group portions of the flash memory into a plurality of logical groups based at least in part on a number of Program/Erase (P/E) cycles;
- monitor command performance latency for each logical group of the plurality of logical groups;
- based on the monitored command performance latency for each logical group, set at least one polling time for each respective logical group of the plurality of logical groups, wherein the at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command;
- and
- set an interval polling time less frequently than setting an initial polling time, wherein the initial polling time indicates a time to wait before initially checking whether a portion of the flash memory in the logical group has completed the command, and the interval polling time indicates a time to wait after initially checking whether the portion of the flash memory in the logical group has completed the command and determining that the portion of the flash memory has not completed the command.
A Data Storage Device (DSD), comprising:
- a flash memory for storing data;
- and
- a controller configured to:
- group portions of the flash memory into a plurality of logical groups based at least in part on a number of Program/Erase (P/E) cycles;
- monitor command performance latency for each logical group of the plurality of logical groups;
- based on the monitored command performance latency for each logical group, set at least one polling time for each respective logical group of the plurality of logical groups, wherein the at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command;
- calculate a mean command performance latency for the logical group;
- calculate a standard deviation in the command performance latency for the logical group;
- estimate a corrected mean command performance latency for the logical group by subtracting the calculated standard deviation from the mean command performance latency;
- and
- set the estimated corrected mean command performance latency as an initial polling time indicating a time to wait before initially checking whether a portion of the flash memory in the logical group has completed the command.
Dependencies are inferred from the claim text.