Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations
AssigneeInternational Business Machines Corporation
InventorsEdward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
Life of this patent
Estimating the term…
Abstract
A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
Claims20
A computer system for facilitating processing within a computing environment, the computer system comprising:
- a memory;
- and
- a memory controller in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
- obtaining, by the memory controller from an input/output (I/O) device coupled to the memory controller via an I/O network, the memory controller being external to the I/O network, a set of memory access operations, the set of memory access operations comprising a plurality of memory access operations to be chained, wherein the plurality of memory access operations are received as a group and are to be processed as an atomic unit;
- executing the plurality of memory access operations in a particular order;
- and
- providing one or more results of the set of memory access operations.
A computer program product for facilitating processing within a computing environment, the computer program product comprising:
- at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
- obtaining, by the memory controller from an input/output (I/O) device coupled to the memory controller via an I/O network, a set of memory access operations, the set of memory access operations comprising a plurality of memory access operations to be chained, wherein the plurality of memory access operations are received as a group and are to be processed as an atomic unit;
- executing the plurality of memory access operations in a particular order;
- and
- providing one or more results of the set of memory access operations.
A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:
- obtaining, by the memory controller from an input/output (I/O) device coupled to the memory controller via an I/O network, the memory controller being external to the I/O network, a set of memory access operations, the set of memory access operations comprising a plurality of memory access operations to be chained, wherein the plurality of memory access operations are received as a group and are to be processed as an atomic unit;
- executing the plurality of memory access operations in a particular order;
- and
- providing one or more results of the set of memory access operations.
Dependencies are inferred from the claim text.