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US 10,949,096 B2Granted
Method using logical based addressing for latency reduction
AssigneeWestern Digital Technologies, Inc.
InventorsDarin Edward Gerhart, Nicholas Edward Ortmeier, Mark David Erickson
Life of this patent
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Abstract
A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
Claims19
A data storage device configured to be coupled to a host, comprising:
- an interface capable of operating in accordance with one or more of the following protocols:
- advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), fibre channel arbitrated loop (FCAL), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, PCIe, or non-volatile memory express (NVMe);
- a memory device;
- and
- a controller configured to:
- receive a host read command of a requested data that has been dispatched to a flash translation layer of the data storage device, wherein the data storage device is operating at a first latency;
- perform a read flow operation based on the host read command of the requested data;
- populate at least one data frame header of a data frame with logical block address latency information of the requested data in an existing reserved field, wherein the logical block address latency information is determined based on an elapsed time between a first timestamp and a second timestamp, and wherein the first timestamp is associated with receiving the host read command and the second timestamp is associated with performing the read flow operation;
- initiate a data transfer for one of transmitting and receiving data to the data storage device;
- read the at least one data frame header;
- operate the data storage device at a second latency, different than the first latency, based on the at least one data frame header;
- and
- transmit the at least one data frame header with the requested data to the host through the interface based on the second latency.
10 more elements
An arrangement comprising:
- an interface capable of operating in accordance with one or more of the following protocols:
- advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), fibre channel arbitrated loop (FCAL), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, PCIe, or non-volatile memory express (NVMe), wherein the interface is capable of operating at a first latency;
- means for performing a read flow operation on a data storage buffer memory based on a host read command from a host of a requested data;
- means for populating at least one data frame header with logical block address latency information of the requested data in an existing reserved field, wherein the logical block address latency information is determined based on an elapsed time between a first timestamp and a second timestamp, and wherein the first timestamp is associated with a means for receiving the host read command and the second timestamp is associated with the means for performing the read flow operation;
- means for initiating a data path transfer for one of transmitting and receiving data to a data storage device;
- means for reading the at least one data frame header;
- means for modifying the data storage buffer memory such that the data storage device operates at a second latency, different than the first latency, based on the at least one data frame header;
- and
- means for transmitting the at least one data frame header with the requested data to the host through the interface based on the second latency.
6 more elements
A data storage device, comprising:
- an interface capable of operating in accordance with one or more of the following protocols:
- advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), fibre channel arbitrated loop (FCAL), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, PCIe, or non-volatile memory express (NVMe);
- a memory;
- and
- a controller configured to:
- receive a host read command from a host of a requested data by a flash translation layer of the data storage device operating at a first latency;
- perform a read flow operation on the memory of the data storage device based on the host read command of the requested data;
- populate at least one data frame header with logical block address latency information of the requested data in an existing reserved field, wherein the logical block address latency information is determined based on an elapsed time between a first timestamp and a second timestamp, and wherein the first timestamp is associated with receiving the host read command and the second timestamp is associated with an action performed associated with the host read command;
- operate the data storage device at a second latency, different than the first latency, based on the at least one data frame header;
- and
- transmit the at least one data frame header with the requested data to the host through the interface.
8 more elements
Dependencies are inferred from the claim text.