Storage device and operating method of storage device
AssigneeSamsung Electronics Co., Ltd.
InventorsHan-Ju Lee, Youngkwang Yoo, Youngjin Cho
Life of this patent
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Abstract
A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.
Claims14
A nonvolatile memory module comprising:
- a plurality of nonvolatile memories;
- and
- a device controller controlling the nonvolatile memories, wherein
- the device controller comprises:
- a random access memory (RAM) inputting and outputting data, the RAM includes:
- a write data area storing data to be written in the nonvolatile memories;
- a command area receiving a nonvolatile memory command for controlling the nonvolatile memories;
- a status area storing information indicating a state of the RAM;
- and
- a read data area storing data read from the nonvolatile memories;
- a command parser receiving and recognizing a command from an external host;
- and
- a process, voltage, temperature (PVT) compensation unit performing a PVT compensation operation in response to a refresh command or a precharge command recognized by the command parser.
A computing system comprising:
- a processor;
- at least one dual in-line memory module connected to the processor through a first double data rate (DDR) slot;
- and
- at least one nonvolatile memory module connected to the processor through a second DDR slot, wherein:
- the at least one nonvolatile memory module performs a PVT compensation operation in response to a refresh command or a precharge command received from the processor,
- the at least one nonvolatile memory module comprises:
- at least one buffer memory;
- a plurality of nonvolatile memories;
- and
- a device controller controlling the at least one buffer memory and the nonvolatile memories, and
- the device controller comprises:
- a physical layer receiving and outputting data through a DDR interface from and to the processor and performing a PVT compensation operation;
- and
- a memory controller receiving and outputting data of the physical layer through a memory interface.
A nonvolatile memory module comprising:
- a plurality of nonvolatile memories;
- and
- a device controller controlling the nonvolatile memories, wherein:
- the device controller comprises:
- a random access memory (RAM) inputting and outputting data,
- a command parser receiving and recognizing a command from an external host, and
- a process, voltage, temperature (PVT) compensation unit performing a PVT compensation operation in response to a refresh command or a precharge command recognized by the command parser;
- and
- the PVT compensation unit determines a delay of a data signal or a data strobe signal by adjusting delay-tap delay cells in response to the refresh command or the precharge command.
Dependencies are inferred from the claim text.