Memory system with block rearrangement to secure a free block based on read valid first and second data
AssigneeToshiba Memory Corporation
InventorsAtsushi Kunimatsu, Kenichi Maeda
Life of this patent
Estimating the term…
Abstract
A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
Claims19
A memory system comprising:
- an interface circuit configured to communicate with a host device, the host device including a first semiconductor memory;
- a second semiconductor memory including a plurality of blocks including a first block, a second block, and a third block, each of the blocks being a unit of an erase operation of the second semiconductor memory, the second semiconductor memory being nonvolatile;
- and
- a controller circuit configured to, in a case that a block rearrangement to secure a free block is executed in the memory system,
- read a valid first data from the first block,
- write the read first data into an area of the first semiconductor memory of the host device, the area having been designated by the host device for storing data from the memory system,
- read a valid second data from the second block,
- write the read second data into the area of the first semiconductor memory,
- read the first data and the second data from the area of the first semiconductor memory, and
- write the read first data and the read second data into the third block.
A storage system comprising:
- a host device including a first semiconductor memory;
- and
- a memory system configured to communicate with the host device, the memory system comprising:
- a second semiconductor memory including a plurality of blocks including a first block, a second block and a third block, each of the blocks being a unit of an erase operation of the second semiconductor memory, the second semiconductor memory being nonvolatile;
- and
- a controller circuit configured to, in a case that a block rearrangement to secure a free block is executed in the memory system,
- read a valid first data from the first block,
- write the read first data into an area of the first semiconductor memory of the host device, the area having been designated by the host device for storing data from the memory system,
- read a valid second data from the second block,
- write the read second data into the area of the first semiconductor memory,
- read the first data and the second data from the area of the first semiconductor memory, and
- write the read first data and the read second data into the third block.
A method for a memory system capable of communicating with a host device having a first semiconductor memory, the memory system including a second semiconductor memory including a plurality of blocks including a first block, a second block, and a third block, each of the blocks being a unit of an erase operation of the second semiconductor memory, the second semiconductor memory being nonvolatile, the method comprising:
- executing a process of, in a case that a block rearrangement to secure a free block is executed in the memory system:
- reading a valid first data from the first block;
- writing the read first data into an area of the first semiconductor memory of the host device, the area having been designated by the host device for storing data from the memory system;
- reading a valid second data from the second block;
- writing the read second data into the area of the first semiconductor memory;
- reading the first data and the second data from the area of the first semiconductor memory;
- and
- writing the read first data and the read second data into the third block.
Dependencies are inferred from the claim text.