Memory controllers, memory systems, solid state drives and methods for processing a number of commands
AssigneeMicron Technology, Inc.
InventorsMehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
Life of this patent
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Abstract
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
Claims22
A method of processing a number of commands, comprising:
- receiving a number of task files each including at least one command from a host in an order;
- performing, using hardware circuitry couplable to the host, an integrity check on the at least one command to verify at least one of a logical block address range or a valid command tag associated with the at least one command;
- and
- processing the at least one command associated with a payload involving more than one of a plurality of back end channels of a memory controller.
An apparatus, comprising:
- a plurality of memory devices;
- and
- a controller coupled to the plurality of memory devices and configured to:
- receive a number of task files each including at least one command from a host in an order;
- perform an integrity check on the at least one command to verify at least one of a logical block address range or a valid command tag associated with the at least one command;
- and
- process the at least one command associated with a payload involving more than one of a plurality of back end channels of the memory controller.
A system, comprising:
- a host;
- a number of memory devices;
- and
- a controller comprising:
- a front end direct memory access module (DMA);
- a command dispatcher coupled to the front end DMA;
- and
- a plurality of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA, wherein the controller is configured to:
- receive a number of task files each including at least one command from the host in an order;
- cause the command dispatcher to perform an integrity check on the at least one command to verify at least one of a logical block address range or a valid command tag associated with the at least one command;
- and
- process the at least one command associated with a payload involving more than one of the number of back end channels.
A method of processing a number of commands, comprising:
- receiving a number of commands from a host in an order;
- processing at least one command associated with a payload involving more than one of a plurality of back end channels of a memory controller;
- determining an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command;
- and
- modifying the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.
An apparatus, comprising:
- a plurality of memory devices;
- and
- a controller coupled to the plurality of memory devices and configured to:
- receive a number of commands from a host in an order;
- and
- process at least one command associated with a payload involving more than one of a plurality of back end channels of the memory controller;
- determine an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command;
- and
- modify the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.
Dependencies are inferred from the claim text.