US 10,948,538 B2 · Register for at-speed scan testing

Abstract

An integrated circuit (IC) has scan chains of stitched registers that support scan testing of functional logic. The scan testing has a shift phase in which incoming and outgoing data are shifted into and out of the registers using a slow clock and a capture phase in which outgoing data from the functional logic is captured by the registers using launch-and-capture pulses of a fast clock to check for delay faults. During a warm-up period after termination of the slow clock but before application of the launch-and-capture pulses, the registers propagate data through their master latches without affecting the data stored in their slave latches. A warm-up controller configures the registers and generates control signals to perform either launch-on-shift or launch-on-capture scan testing. The flow of data and the warm-up controller operations keep the power supply rail voltage sufficiently charged for the fast launch-and-capture pulses.

Claims13

Dependent claims

An integrated circuit, comprising:

functional logic that processes incoming data and generates corresponding outgoing data;
and
registers stitched into a scan chain that supports scan testing of the functional logic, wherein:
each register comprises a master latch followed by a slave latch;
and
each register supports (i) a first configuration in which the slave latch is connected to a first output of the register and (ii) a warm-up configuration in which a node in the master latch is connected directly to the first output of the register bypassing the slave latch;
a warm-up controller that generates a warmup-select control signal that determines whether each register is configured in the first configuration or in the warm-up configuration;
wherein the warm-up controller generates a scan-enable control signal (SE) that determines whether each register selects data from the register's SDI input or the register's D input for launching a transition at a launch pulse of a capture phase of at-speed scan testing.

5 more elements

An integrated circuit, comprising:

functional logic that processes incoming data and generates corresponding outgoing data;
and
registers stitched into a scan chain that supports scan testing of the functional logic, wherein:
each register comprises a master latch followed by a slave latch;
and
each register supports (i) a first configuration in which the slave latch is connected to a first output of the register and (ii) a warm-up configuration in which a node in the master latch is connected directly to the first output of the register bypassing the slave latch;
wherein:
when the registers are configured in the warm-up configuration, a combinational flow of data propagates through the master latches without affecting data stored in the slave latches;
the master latch of each register comprises a pair of inverters through which the combinational flow of data propagates when the register is configured in the warm-up configuration;
the scan testing comprises a shift phase followed by a capture phase;
during the shift phase, using a slower clock, at least one of (i) incoming scan test data is shifted into the registers and (ii) outgoing scan test data is shifted out of the registers;
during the capture phase, using launch and capture pulses of a faster clock, the outgoing scan test data from the functional logic under test is captured by the registers;
during a warm-up period after termination of the slower clock and before application of the launch and capture pulses, the registers are configured in the warm-up configuration;
during the warm-up period, the registers in the scan chain are not clocked;
each register comprises a pair of switches selectively connecting the register's first output to either the slave latch or the node in the master latch;
the integrated circuit further comprises a warm-up controller that generates a warmup-select control signal that determines whether each register is configured in the normal configuration or in the warm-up configuration;
the warm-up controller comprises counters that count warm-up pulses to determine when to change the warmup-select control signal;
the warm-up controller generates a scan-enable control signal that determines whether each register selects data from the register's SDI input or the register's D input for launching a transition at the launch pulse of the capture phase of at-speed scan testing;
the warm-up controller selectively generates the scan-enable control signal to support either launch-on-shift (LOS) scan testing or launch-on-capture (LOC) scan testing;
and
the warm-up controller comprises counters that count warm-up pulses to determine when to change the scan-enable control signal.

18 more elements

Dependencies are inferred from the claim text.

Register for at-speed scan testing

Life of this patent

Register for at-speed scan testing

Life of this patent

Abstract

Claims13