Radar level indicator having a short measurement time
AssigneeVEGA Grieshaber KG
InventorsRoland Welle, Joerg Boersig, Karl Griessbaum
Life of this patent
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Abstract
A radar level indicator comprising a processor, an analogue-digital converter circuit and an intermediate memory connected therebetween. The intermediate memory is configured to receive digital signals from the analogue-digital converter circuit at a first data rate. The processor is configured to read out the intermediate memory at a second data rate that is different from the first data rate. It is thus possible to reduce the transmission time while maintaining the same energy requirement.
Claims15
A method for fill level measurement, limit measurement, pressure measurement or flow measurement, in which measurement data are acquired and processed, said method comprising:
- acquiring fill level, limit level, pressure or flow measurement data;
- activating an intermediate memory by supplying the intermediate memory with an external operating clock signal and/or supply voltage;
- receiving, in the intermediate memory, digital signals from an analogue-digital converter circuit at a first data rate, the digital signals corresponding to the acquired fill level, limit level, pressure or flow measurement data;
- activating a processor after receiving the digital signals in the intermediate memory;
- reading out, by the processor, data from the intermediate memory at a second data rate that is smaller than the first data rate;
- deactivating the intermediate memory by separating the intermediate memory from the external operating clock signal and/or the external supply voltage;
- calculating, by the processor and after deactivating the intermediate memory, a measured value from the digital signals and outputting the measured value;
- putting the processor into a sleep mode;
- and
- activating the intermediate memory.
A radar level indicator, comprising:
- at least one processor;
- at least one analogue-digital converter circuit;
- and
- at least one intermediate memory that is arranged between the processor and the analogue-digital converter circuit,
- wherein the intermediate memory is activated by a supplied external operating clock signal and/or supply voltage and deactivated by separating the intermediate memory from the external operating clock signal and/or the external supply voltage,
- wherein the intermediate memory is configured to receive digital signals from the analogue-digital converter circuit at a first data rate, the digital signals corresponding to acquired fill level, limit level, pressure or flow measurement data,
- wherein the processor is configured to read out the intermediate memory at a second data rate that is smaller than the first data rate,
- wherein the processor is configured to, after the intermediate memory is deactivated, calculate a measured value from the digital signals and output the measured value, and
- wherein the processor is put into a sleep mode and the intermediate memory is activated in response to the output of the measured value.
A method for fill level measurement, limit measurement, pressure measurement or flow measurement, in which measurement data are acquired and processed, said method comprising:
- acquiring fill level, limit level, pressure or flow measurement data;
- in response to the acquiring, activating an intermediate memory by supplying the intermediate memory with an external operating clock signal and/or supply voltage;
- receiving, in the intermediate memory, digital signals from an analogue-digital converter circuit at a first data rate, the digital signals corresponding to the acquired fill level, limit level, pressure or flow measurement data;
- in response to the receiving the digital signals in the intermediate memory, activating a processor;
- reading out, by the processor, data of the digital signals from the intermediate memory at a second data rate that is lower than the first data rate;
- in response to the reading out, deactivating the intermediate memory by separating the intermediate memory from the external operating clock signal and/or the external supply voltage;
- calculating, by the processor and after deactivating the intermediate memory, a measured value from the digital signals and outputting the measured value;
- and
- in response to the outputting, putting the processor into a sleep mode and activating the intermediate memory.
Dependencies are inferred from the claim text.