Core tightly coupled lockstep for high functional safety

One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to cause:

• a master core, coupled to a slave core, to execute one or more operations to support Advanced Driver Assistance Systems(ADA) or autonomous driving, wherein the master core and the slave core are to receive the same input signals;
• core tightly couple logic to cause generation of a signal in response to comparison of a first output from the master core and a second output from the slave core, wherein the signal is to cause an interruption of the one or more operations in response to a mismatch between the first output and the second output,
• wherein a lock-stepped domain comprises the master core and the slave core and a non-deterministic domain comprises one or more memory controllers and one or more coherency controllers coupled to the one or more memory controllers;
• and
• Uncore Functional Safety Mechanism (UCFS) logic to communicatively couple the lock-stepped domain and the non-deterministic domain to drive the input signals to both the master core and the slave core.

A computing system comprising:

• a processor having one or more processor cores;
• memory, coupled to the processor, to store one or more bits of data;
• the one or more processor cores comprising a master core, coupled to a slave core, to execute one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving, wherein the master core and the slave core are to receive the same input signals;
• core tightly couple logic to cause generation of a signal in response to comparison of a first output from the master core and a second output from the slave core, wherein the signal is to cause an interruption of the one or more operations in response to a mismatch between the first output and the second output,
• wherein a lock-stepped domain comprises the master core and the slave core and a non-deterministic domain comprises one or more memory controllers and one or more coherency controllers coupled to the one or more memory controllers;
• and
• Uncore Functional Safety Mechanism (UCFS) logic to communicatively couple the lock-stepped domain and the non-deterministic domain to drive the input signals to both the master core and the slave core.