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US 10,944,922 B2Granted
Hybrid output multiplexer for a high framerate CMOS imager
AssigneeGvbb Holdings S.A.R.L.
InventorsJeroen Rotte, Juul Josephus Johannes Van Den Heijkant, Rik Visser
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Abstract
An imaging system is provided that includes a pixel array having a plurality of columns with rows of pixels and with each pixel having a plurality of photodiodes and a common readout circuit that stores respective accumulation voltages from each of the plurality of photodiodes. Moreover, the system includes row driver circuitry that control the pixel array for pixel addressing and readout, such that the respective accumulation voltages of the photodiodes is read out on a readout channel coupled to a bit line column, and a hybrid multiplexer that multiplexes and routes output signals from the pixel array to a video imaging device to be displayed thereon.
Claims17
An imaging system comprising:
- a pixel array including a plurality of columns having a plurality of rows of pixels, with each pixel having a plurality of photodiodes and a common readout circuit configured to store respective accumulation voltages from each of the plurality of photodiodes;
- row driver circuitry configured control the pixel array for pixel addressing and readout;
- an image sensor controller configured to control the row driver circuitry to address the plurality of rows of pixels in the pixel array, such that the respective accumulation voltages of at least a portion of photodiodes of the plurality of rows is concurrently read out on a readout channel coupled to at least one bit line column;
- a plurality of analog to digital converters coupled to the at least one bit line column and configured to convert output signals from the pixel array to a plurality of digital signals that correspond to the respective accumulation voltages of the at least portion of photodiodes of the plurality of rows;
- and
- a hybrid multiplexer configured to multiplex and route the plurality of digital signals to a video imaging device to be displayed thereon,
- wherein the hybrid multiplexer comprises:
- a first stage including a plurality of tristate multiplexers;
- a second stage including a plurality of registers configured to receive digital output signals from the first stage and store values therein;
- and
- a third stage including at least one digital multiplexer coupled to the plurality of registers and configured to serially route the digital output signals from the second stage to a control unit for producing a digital image of image data captured by the pixel array on the video imaging device,
- wherein the second stage of the hybrid multiplexer is configured to store the digital output signals to provide a settling time for the first stage to receive a next value of the plurality of digital signals output from the plurality of analog to digital converters,
- wherein the third stage of the hybrid multiplexer is configured to daisy chain the respective outputs of the first and second stages to multiplex the plurality of digital signals to the control unit,
- wherein the first stage of the hybrid multiplexer includes a plurality of 11:1 tristate multiplexers, and
- wherein the third stage of the hybrid multiplexer includes at least one 6:1 digital multiplexer.
12 more elements
An imaging system comprising:
- a pixel array including a plurality of columns having a plurality of rows of pixels, with each pixel having a plurality of photodiodes and a common readout circuit configured to store respective accumulation voltages from each of the plurality of photodiodes;
- row driver circuitry configured control the pixel array for pixel addressing and readout, such that the respective accumulation voltages of at least a portion of photodiodes of the plurality of rows is concurrently read out on a readout channel coupled to at least one bit line column;
- a plurality of analog to digital converters coupled to the at least one bit line column and configured to convert output signals from the pixel array to a plurality of digital signals that correspond to the respective accumulation voltages of the at least portion of photodiodes of the plurality of rows;
- and
- a hybrid multiplexer configured to multiplex and route the plurality of digital signals to a video imaging device to be displayed thereon,
- wherein the hybrid multiplexer comprises:
- a first stage including a plurality of tristate multiplexers;
- a second stage including a plurality of registers configured to receive digital output signals from the first stage and store values therein;
- and
- a third stage including at least one digital multiplexer coupled to the plurality of registers and configured to serially route the digital output signals from the second stage to a control unit for producing a digital image of image data captured by the pixel array on the video imaging device,
- wherein the second stage of the hybrid multiplexer is configured to store the digital output signals to provide a settling time for the first stage to receive a next value of the plurality of digital signals output from the plurality of analog to digital converters.
8 more elements
An imaging system comprising:
- a pixel array including a plurality of columns having a plurality of rows of pixels, with each pixel having a plurality of photodiodes and a common readout circuit configured to store respective accumulation voltages from each of the plurality of photodiodes;
- row driver circuitry configured control the pixel array for pixel addressing and readout, such that the respective accumulation voltages of at least a portion of photodiodes of the plurality of rows is read out on a readout channel coupled to at least one bit line column;
- a hybrid multiplexer configured to multiplex and route a plurality of output signals from the pixel array to a video imaging device to be displayed thereon, wherein the hybrid multiplexer comprises:
- a first stage including a plurality of tristate multiplexers;
- a second stage including a plurality of registers configured to receive digital output signals from the first stage and store values therein;
- and
- a third stage including at least one digital multiplexer coupled to the plurality of registers and configured to serially route the digital output signals from the second stage to a control unit for producing a digital image of image data captured by the pixel array on the video imaging device.
4 more elements
Dependencies are inferred from the claim text.