Phase-locked loop and delay-locked loop

A phase-locked loop which alternately operates in a sleep state and an active state,

• wherein a frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal,
• when the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state,
• wherein information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a memory device,
• wherein the phase-locked loop comprises:
• a reference signal frequency divider configured to divide a frequency of a reference signal;
• and
• an output signal frequency divider configured to divide a frequency of an output signal of the phase-locked loop,
• wherein the frequency-divided output signal is synchronized with the frequency-divided reference signal,
• wherein a sleep signal is provided to control the sleep state and the active state of the phase-locked loop, and
• wherein the phase-locked loop further comprises:
• a synchronizer configured to receive the sleep signal and generate a reference signal frequency divider activation signal for activating the reference signal frequency divider and an output signal frequency divider activation signal for activating the output signal frequency divider.