Frequency doubler based on phase frequency detectors using rising edge delay

A method of doubling a frequency of an input clock signal, the method comprising:

• delaying the input clock signal by a first delay to generate a delayed clock signal;
• inverting and delaying the input clock signal by a second delay to generate a complementary delayed clock signal;
• applying a first adjustable delay to rising edges only of the delayed clock signal to generate a first rising-edge-delayed clock signal;
• applying a second adjustable delay to rising edges only of the complementary delayed clock signal to generate a second rising-edge-delayed clock signal;
• determining differences between rising edges of the delayed clock signal and the first rising-edge-delayed clock signal to generate a first rising-edge-difference signal;
• determining differences between rising edges of the complementary delayed clock signal and the second rising-edge-delayed clock signal to generate a second rising-edge-difference signal;
• combining the first and second rising-edge-difference signals to generate a combined signal;
• comparing a direct-current (DC) voltage value of the combined signal with a reference voltage;
• and
• controlling the first adjustable delay and the second adjustable delay based on the comparison.

An apparatus for doubling a frequency of an input clock signal, the apparatus comprising:

• means for delaying the input clock signal by a first delay to generate a delayed clock signal;
• means for inverting and delaying the input clock signal by a second delay to generate a complementary delayed clock signal;
• means for applying a first adjustable delay to rising edges only of the delayed clock signal to generate a first rising-edge-delayed clock signal;
• means for applying a second adjustable delay to rising edges only of the complementary delayed clock signal to generate a second rising-edge-delayed clock signal;
• means for determining differences between rising edges of the delayed clock signal and the first rising-edge-delayed clock signal to generate a first rising-edge-difference signal;
• means for determining differences between rising edges of the complementary delayed clock signal and the second rising-edge-delayed clock signal to generate a second rising-edge-difference signal;
• means for combining the first and second rising-edge-difference signals to generate a combined signal;
• means for comparing a direct-current (DC) voltage value of the combined signal with a reference voltage;
• and
• means for controlling the first adjustable delay and the second adjustable delay based on the comparison.