Semiconductor devices, hybrid transistors, and related methods
AssigneeMicron Technology, Inc.
InventorsKamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy
Life of this patent
Estimating the term…
Abstract
A semiconductor device is disclosed. The semiconductor device includes a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material. Memory arrays, semiconductor devices, and systems incorporating memory cells, and hybrid transistors are also disclosed, as well as related methods for forming and operating such devices.
Claims26
A semiconductor device, comprising:
- a hybrid transistor including:
- a gate electrode;
- a drain material;
- a source material;
- and
- a channel region comprising a channel material operatively coupled between the drain material and the source material, wherein the source material and the drain material include a low bandgap high mobility material relative to the channel material that is a high bandgap low mobility material, and wherein the channel region is a hybrid channel region further including another low bandgap high mobility material disposed between opposing portions of the high bandgap low mobility material.
A semiconductor device, comprising:
- a hybrid transistor comprising:
- a channel region defined by a length of an adjacent gate electrode, the channel region including at least a high bandgap low mobility material;
- and
- a drain region and a source region disposed on opposing ends of the channel region, the drain region and the source region each including at least a low bandgap high mobility material,
- wherein the channel region is a hybrid channel region including another low bandgap high mobility material disposed between opposing portions of the high bandgap low mobility material.
A method of operating a memory cell, the method comprising enabling a hybrid transistor by applying a gate voltage to a gate electrode to cause a drive current to flow through a channel region coupled between a source region and a drain region, the channel region including a high bandgap low mobility material relative to the source region and drain region each including a low bandgap high mobility material, the channel region further including another low bandgap high mobility material disposed between opposing portions of the high bandgap low mobility material.
Dependencies are inferred from the claim text.