Memory processing unit

An in-memory computing method for performing multiply-accumulate (MAC) operations and computing vector-matrix multiplications, the method comprising:

• applying data values of a first vector as inputs to a set of wordlines of an array of resistive memory devices arranged in columns and rows, wherein the array is arranged such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, and wherein each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein;
• computing vector-matrix multiplication between the data values of the first vector applied as inputs to the given set of wordlines and the data values of a second vector stored in the array of resistive memory devices by, for each given bitline:
• receiving, by a comparator directly connected to a corresponding bitline, outputs on the given bitline in response to the inputs being applied to the set of wordlines;
• comparing, by the comparator directly connected to the corresponding bitline, the outputs from the given bitline to a threshold associated with the respective comparator;
• and
• incrementing, by a counter directly connected to a corresponding comparator, a count for the given bitline when the comparison of the output for the given bitline exceeds the threshold, such that the count of the given bitline performs the MAC operation between the data values of the first vector as inputs applied to the set of wordlines and the second vector stored in the array of resistive memory devices.

An in-memory computing system for performing multiple-accumulate (MAC) operations and computing vector-matrix multiplications, the in-memory computing system comprising:

• an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value;
• and
• an interface circuit electrically coupled to each bitline of the array of resistive memory devices and cooperatively operates with the array of resistive memory devices to compute a vector-matrix multiplication between data values of a first vector as inputs applied to a set of wordlines and data values of a second vector stored in the array of resistive memory devices, where the interface circuit, for each given bitline:
• receives outputs on the given bitline in response to the inputs being applied to the set of wordlines;
• and
• compares the outputs from the given bitline to a threshold;
• and
• wherein the interface circuit comprises a plurality of counters, wherein each counter of the plurality of counters is electrically connected to a corresponding bitline, and wherein each counter increments a count maintained for the given bitline when the comparison of the output for the given bitline exceeds the threshold, such that the count for the given bitline represents the MAC operation performed between the data values of the first vector as inputs applied to the set of wordlines and the second vector stored in the array of resistive memory devices.