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US 10,937,907 B2Granted
Method for fabricating transistor with thinned channel
AssigneeIntel Corporation
InventorsJustin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
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Abstract
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Claims20
An apparatus comprising:
- a first portion of a semiconductor body, wherein the first portion is under a gate electrode, and wherein the first portion has a first width, wherein the gate electrode is a tri-gate structure;
- and
- a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width, and wherein the semiconductor body is a fin on a substrate;
- and
- a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, and
- wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV, and wherein the gate electrode is of an n-type device.
3 more elements
A system comprising:
- a memory;
- a processor;
- and
- a network interface coupled to the processor via a bus, wherein the processor is at least one of:
- a central processing unit (CPU);
- a graphics processor;
- a digital signal processor;
- or a crypto processor, wherein the memory comprises at least one of a volatile memory or non-volatile memory, and wherein the processor includes:
- a first portion of a semiconductor body, wherein the first portion is under a gate electrode, wherein the first portion has a first width, and wherein the gate electrode is a tri-gate structure;
- and
- a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width, and wherein the semiconductor body is a fin on a substrate;
- and
- a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV, and wherein the gate electrode is of an n-type device.
10 more elements
A method comprising:
- forming a first portion of a semiconductor body, wherein the first portion is under a gate electrode, wherein the first portion has a first width, and wherein the gate electrode is a tri-gate structure;
- and
- forming a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width, and wherein the semiconductor body is a fin on a substrate;
- and
- forming a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV, and wherein the gate electrode is of an n-type device.
2 more elements
Dependencies are inferred from the claim text.