Nanosheet eDRAM

A semiconductor structure comprising:

• a nanosheet device comprising a plurality of stacked and suspended semiconductor channel material nanosheets located above a topmost semiconductor layer of a semiconductor-on-insulator (SOI) substrate, a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets, and a source/drain (S/D) region composed of a doped single crystalline semiconductor material located on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
• an embedded dynamic access memory (eDRAM) cell located laterally adjacent to the nanosheet device and located in a trench that is present in the SOI substrate;
• a strap composed of a doped polycrystalline semiconductor material connecting a polycrystalline semiconductor material electrode of the eDRAM cell to one of the S/D regions of the nanosheet device;
• and
• a collar dielectric material located entirely above a topmost surface of the polycrystalline semiconductor material electrode and on sidewalls of an upper portion of the trench, wherein the strap directly contacts a topmost surface of the collar dielectric material, a topmost surface of the polycrystalline semiconductor material electrode, an entirety of a sidewall of the collar dielectric material, and an entirety of a sidewall of the one of the S/D regions that the strap is connected to.