Integrated ultralong time constant time measurement device and fabrication process
AssigneeSTMicroelectronics (Rousset) SAS
InventorsAbderrezak Marzaki, Pascal Fornara
Life of this patent
Estimating the term…
Abstract
An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
Claims11
An ultralong time constant time measurement device, comprising:
- a plurality of elementary capacitive elements connected in a series;
- a capacitive storage element that is connected to one end of the series connected plurality of elementary capacitive elements and is configured to be charged;
- wherein the series connected plurality of elementary capacitive elements is configured to discharge the charged capacitive storage element and to deliver, to at least one node of the series connected plurality of elementary capacitive elements, a physical quantity that is representative of the discharging of the capacitive storage element and a duration that has elapsed between a start of an operation of discharging the capacitive storage element and a time at which the physical quantity is delivered;
- wherein each elementary capacitive element comprises:
- a stack of a first conductive region, a dielectric layer having a thickness that allows charge to flow by direct tunneling effect and a second conductive region,
- wherein the first conductive region is housed in a trench extending from a front face of a semiconductor substrate into the semiconductor substrate, and
- wherein the dielectric layer rests on the front face of the semiconductor substrate and the second conductive region rests on the dielectric layer.
Dependencies are inferred from the claim text.