Apparatuses and methods to encode column plane compression data

An apparatus comprising:

• a compare circuit configured to receive, during a test operation, a plurality of column plane read data bits each associated with a respective column plane of a memory cell array, wherein the compare circuit is further configured to detect Whether a value of a bit of the plurality of column plane read data bits is different than an expected value and to provide error data based on the detection and based on the respective column plane of the memory cell array with which the bit is associated;
• and
• an encoder circuit configured to encode a column plane error code based on the error data for provision to a data terminal, wherein the encoder circuit is configured to, in response to the error data indicating that the value of the bit of the plurality of column plane read data bits is different than the expected value and is associated with a first column plane:
• encode the column plane error code with a first value based on the first column plane the error data indicates all other bits of the plurality of column plane read data bits matched the expected value;
• and
• encode the column plane error code with a second value in response to the error data indicating that the value of a second bit of the plurality of column plane read data bits associated with a second column plane is different than the expected value.

A method comprising:

• receiving, during a test operation at a compression circuit of a semiconductor device, a plurality of column plane read data bits each associated with a respective column plane of a memory cell array of the semiconductor device;
• determining an expected value based on logical bitwise comparisons between the plurality of column plane read data bits;
• detecting whether a value of a bit of the plurality of column plane read data bits is different than the expected value;
• encoding a column plane error code based on whether the value of the bit of the plurality of column plane read data bits is detected to have the value different than the expected value and based on the respective column plane with which the bit is associated;
• and
• storing the column plane error code at the semiconductor device.

A method, comprising:

• receiving, during a test operation at a compression circuit of a semiconductor device, a plurality of column plane read data bits each associated with a respective column plane of a memory cell array of the semiconductor device;
• detecting whether a value of a bit of the plurality of column plane read data bits is different than an expected value;
• encoding a column plane error code based on whether the value of the bit of the plurality of column plane read data bits is detected to have the value different than the expected value and based on the respective column plane with which the bit is associated;
• storing the column plane error code at the semiconductor device;
• and
• serializing bits of the column plane error code for provision to an output of the semiconductor device, for use by internal logic of the semiconductor device, or any combination thereof.