Embedded pad structures of three-dimensional memory devices and fabrication methods thereof

A 3D memory device, comprising:

• an array device semiconductor structure comprising:
• an alternating conductor/dielectric stack disposed on a semiconductor layer, and
• an array interconnect layer disposed on the alternating conductor/dielectric stack and including at least one first interconnect structure;
• a peripheral device semiconductor structure comprising:
• at least one peripheral device disposed on a substrate, and
• a peripheral interconnect layer disposed on the at least one peripheral device and including at least one second interconnect structure;
• at least one pad embedded in the array device semiconductor structure or the peripheral interconnect layer;
• and
• a pad opening exposing a surface of the at least one pad;
• wherein the array interconnect layer is bonded with the peripheral interconnect layer, and the at least one pad is electrically connected with the at least one peripheral device through the at least one first interconnect structure or the at least one second interconnect structure.