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US 10,930,650 B2Granted
Latch-up immunization techniques for integrated circuits
AssigneeSTMicroelectronics International N.V.
InventorVishal Kumar Sharma
Life of this patent
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Abstract
In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.
Claims32
An integrated circuit, comprising:
- a semiconductor substrate doped with a first conductivity type;
- a first semiconductor well doped with a second conductivity type within the semiconductor substrate and including:
- a first region heavily doped with the second conductivity type, wherein the first region is connected to a supply node;
- and
- a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad;
- a second semiconductor well doped with the second conductivity type within the semiconductor substrate;
- a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a ground node;
- a third semiconductor well doped with the second conductivity type within the semiconductor substrate;
- and
- a fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to the integrated circuit pad through a resistor;
- wherein the third semiconductor well is positioned within the semiconductor substrate between the first semiconductor well and the second semiconductor well.
8 more elements
An integrated circuit, comprising:
- a semiconductor substrate doped with a first conductivity type;
- a first semiconductor well doped with a second conductivity type within the semiconductor substrate and including:
- a first region heavily doped with the second conductivity type, wherein the first region is connected to a supply node;
- and
- a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad;
- a second semiconductor well doped with the second conductivity type within the semiconductor substrate;
- a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to the integrated circuit pad through a resistor;
- and
- a fourth region heavily doped with the second conductivity type within semiconductor substrate, wherein the fourth region is connected to a ground node;
- wherein said second semiconductor well is positioned within the semiconductor substrate between the fourth region and the first semiconductor well.
7 more elements
Dependencies are inferred from the claim text.