Methods for producing nanowire stack GAA device with inner spacer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
Estimating the term…
The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
A method of forming a semiconductor device, the method comprising:
A method of forming a semiconductor device comprising:
Dependencies are inferred from the claim text.