Fixed-level charge sharing type LCV for memory compiler
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAtul Katoch, Adrian Earle
Life of this patent
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Abstract
A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.
Claims20
A memory device, comprising:
- an array of memory cells;
- a bit line connected to the memory cells;
- a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level;
- a bit line precharge circuit having an input terminal configured to receive the power supply voltage at the first voltage level, wherein the bit line precharge circuit is configured to select a second voltage level lower than the first voltage level and precharge the bit line to the second voltage level, the bit line precharge circuit including:
- a first power header having a first switch and configured to selectively connect the plurality of bit lines directly to the power supply voltage terminal;
- and
- a second power header having a trim device and a second switch and configured to selectively connect the plurality of bit lines to the power supply voltage terminal via the trim device;
- and
- a precharge controller configured to actuate the first switch to selectively connect the plurality of bit lines directly to the power supply voltage terminal for a first predetermined time period, and to actuate the second switch to selectively connect the plurality of bit lines to the power supply voltage terminal via the trim device for a second predetermined time period that is shorter than the first predetermined time period.
A bit line precharge circuit, comprising:
- an input terminal configured to receive a power supply voltage at a first voltage level;
- an output terminal configured to output a precharge voltage to a plurality of bit lines of a memory array;
- a first power header having a first switch configured to selectively connect the output terminal directly to the input terminal in response to a first control signal;
- a second power header having a first trim device and a second switch configured to selectively connect the output terminal to the input terminal via the first trim device in response to a second control signal;
- a third power header having a second trim device and a third switch configured to selectively connect the output terminal to the input terminal via the second trim device in response to a third control signal;
- and
- a fourth power header having a third trim device and a fourth switch configured to selectively connect the output terminal to the input terminal via the third trim device in response to a fourth control signal.
A method for pre-charging bit lines of a memory array, comprising:
- connecting a power supply voltage to a plurality of bit lines of a memory array for a first predetermined time period;
- and
- connecting the power supply voltage via a trim device to the bit lines for a second predetermined time period that is shorter than the first predetermined time period to precharge the bit lines at a precharge voltage that is less than the power supply voltage.
Dependencies are inferred from the claim text.