Substrate routing and throughput modeling

A system, comprising:

• a processor;
• and
• a memory having instructions stored thereon, which, when executed by the processor, performs an operation for scheduling a semiconductor substrate processing sequence in an integrated substrate processing system, the operation comprising:
• assigning a sequence of processes to be performed to each semiconductor substrate in a batch of semiconductor substrates to be processed;
• for each processing chamber in the integrated substrate processing system, assigning a processing chamber to each process of the sequence of processes in the batch of semiconductor substrates;
• generating a processing model for the batch of semiconductor substrates, based on the processing chamber assignments;
• generating a timetable for the batch of semiconductor substrates based off the processing model;
• and
• processing the batch of semiconductor substrates in accordance with the timetable.

A non-transitory computer readable medium having instructions stored thereon, which, when executed by a processor, cause the processor to perform a method of scheduling a semiconductor substrate processing sequence in an integrated substrate processing system, comprising:

• assigning a sequence of processes to be performed to each semiconductor substrate in a batch of semiconductor substrates;
• for each processing chamber in the integrated substrate processing system, assigning a processing chamber to each process of the sequence of processes in the batch of semiconductor substrates;
• generating a processing model for the batch of semiconductor substrates based on the processing chamber assignments;
• generating a timetable for the batch of semiconductor substrates based off the processing model;
• and
• processing the batch of semiconductor substrates in accordance with the timetable.