Semiconductor device packages and stacked package assemblies including high density interconnections

A semiconductor device package comprising:

• a conductive post;
• a package body encapsulating portions of the conductive post, wherein the package body includes a front surface and a back surface opposite to the front surface;
• and
• a redistribution stack including
• a dielectric layer disposed over the front surface of the package body and defining a first opening exposing at least a portion of a terminal end of the conductive post;
• and
• an RDL disposed over the dielectric layer and including a first trace,
• wherein the first trace includes a first portion extending over the dielectric layer, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the terminal end of the conductive post,
• wherein a projection area of the first trace onto the terminal end of the conductive post is no greater than 15% of a total area of the terminal end of the conductive post.

A semiconductor device package comprising:

• a package body including a front surface and a back surface opposite to the front surface;
• and
• a redistribution stack adjacent to the front surface of the package body and including
• a first RDL including a first trace;
• a dielectric layer disposed over the first RDL;
• and
• a second RDL including a second trace extending over the dielectric layer and electrically connected to the first trace through the dielectric layer,
• wherein the dielectric layer defines an opening exposing a portion of the first trace, the second trace includes a first portion extending over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion disposed in the opening and extending between the first portion of the second trace and the exposed portion of the first trace, and the second portion of the second trace covers a top surface and opposing side surfaces of the exposed portion of the first trace.

A semiconductor device package comprising:

• a package body including a front surface and a back surface opposite to the front surface;
• and
• a redistribution stack adjacent to the front surface of the package body and including
• an RDL including a first trace;
• a dielectric layer disposed over the RDL;
• and
• an under bump metallization (UBM) disposed over the dielectric layer and electrically connected to the first trace through the dielectric layer,
• wherein a portion of the first trace overlaps a projection area of the UBM onto the RDL,
• wherein the RDL further includes at least two additional traces extending within the projection area of the UBM.

A semiconductor device package comprising:

• a package body including a front surface and a back surface opposite to the front surface;
• and
• a redistribution stack adjacent to the front surface of the package body and including
• a dielectric layer;
• a conductive pad at least partially embedded in the dielectric layer;
• and
• an RDL including a trace extending over the dielectric layer and electrically connected to the conductive pad through an opening in the dielectric layer,
• wherein a projection area of the trace onto the conductive pad is no greater than 15% of a total area of the conductive pad.