Programmable resistance memory on thin film transistor technology
AssigneeAttopsemi Technology Co., LTD
InventorShine C. Chung
Life of this patent
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Abstract
Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.
Claims20
A programmable resistive memory, comprising:
- a plurality of programmable resistive cells, at least one of the cells comprising:
- a programmable resistive element (PRE) having one end coupled to a first supply voltage line;
- a selector having at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a non-single-crystal-silicon semiconductor film on an insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line;
- and
- a gate fabricated on the layer of non-single-crystalline-silicon semiconductor with a sandwich of dielectric in between;
- the gate coupled to a third supply voltage line that can control conductivity between the first and the second active region, and
- wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state.
An electronics system, comprising:
- a processor;
- and
- a programmable resistive memory operatively connected to the processor, the programmable resistive memory including a plurality of programmable resistive cells, at least one of the cells comprising:
- a programmable resistive element (PRE) having one end coupled to a first supply voltage line;
- a selector having at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a non-single-crystal-silicon semiconductor film on an insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line;
- and
- a gate fabricated on the layer of non-single-crystal-silicon semiconductor with a sandwich of dielectric in between, the gate coupled to a third supply voltage line to control the conductivity between the first and the second active region;
- and
- wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state.
A method for operating a programmable resistive memory on a non-single-crystal-silicon semiconductor, the method comprises:
- providing a plurality of programmable resistive cells, at least one of the programmable resistive cells includes at least (i) a programmable resistive element having one end coupled to a first supply voltage line;
- and (ii) a selector having at least one first active region and a second active region, where the first active region having a first type of dopant and the second region having a first or a second type of dopant, both the first and second active regions being fabricated on an insulator substrate, the first active region coupled to the OTP element, and the second active region coupled to a second supply voltage line, (iii) a gate fabricated on the non-crystalline semiconductor with a sandwich of dielectric in between, the gate coupled to a third supply voltage to control the conductivity between the first and the second active regions;
- and
- programming a logic state into at least one of the programmable resistive cells by applying voltages to the first, the second, and/or the third voltage lines.
Dependencies are inferred from the claim text.