Phase measurement

A computer program which, when executed on a computer of circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, causes the circuitry to carry out a method of measuring phase, wherein the circuitry comprises a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along a length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time, the method comprising:

• sampling the delay line at successive sample times based on the second clock signal and recording at each sample time the position of a given signal edge of the first clock signal along the delay line;
• and
• determining a phase angle per delay unit based on successive recorded said positions,
• wherein the delay line is sampled every X cycles of the second clock signal,
• and wherein X is set so that:
• (X*F1)/F2 gives an integer plus fraction result, the fraction of the result indicating a corresponding fraction of a full phase revolution of the first clock signal by which the phase of the first clock signal is expected to advance every X cycles of the second clock signal, the fraction of the full phase revolution of the first clock signal and its complement constituting complementary major and minor portions of the full phase revolution of the first clock signal;
• and
• the fraction of the result is sufficiently larger than 0.5 or sufficiently smaller than 0.5 such that the successive recorded positions follow a repeating pattern, the pattern which repeats comprising the successive recorded positions stepping along the delay line in a given direction in at least 3 relatively-small steps and then returning in an opposite direction via a single relatively-large step, each step traversing consecutive said delay units.

Phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising:

• a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along a length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time;
• an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line;
• and
• a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions,
• wherein the delay line is configured so that its propagation delay is at least as long as an intended period P1 of the first clock signal or an upper end of a given range of values of the period P1, and optionally shorter than 2 times the intended period P1 or the upper end of the given range of values of the period P1.

Phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising:

• a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along a length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time;
• an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line;
• a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions;
• a measured phase relationship determiner configured to determine a measured phase relationship between the first and second clock signals at each of a series of said sample times based on a corresponding recorded positions and the phase angle per delay unit;
• a target phase relationship determiner configured to determine a target phase relationship between the first and second clock signals at each of the or a series of sample times based on those sample times, F1 and F2;
• and
• a phase error determiner configured to determine a phase error between the first and second signals based on the measured phase relationships and the corresponding target phase relationships.