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US 10,904,048 B2Granted
Pulse width modulated receiver systems and methods
AssigneeSanDiskTechnologies LLC
InventorSaravanakumar Durairaj
Life of this patent
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Abstract
A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.
Claims18
A pulse-width demodulator for non-volatile memory timing, comprising:
- a first integrator leg to charge to a voltage reference in response to receipt of a differential data signal;
- a second integrator leg to charge to a charge level with a first signal of the differential data signal being at a first level and output a pulse width modulation voltage, the charge level being based on an amount of time in which the first signal is at the first level;
- a comparator to receive the voltage reference and the pulse width modulation voltage and to output a low output signal with the pulse width modulation voltage being less than the voltage reference and output a high output signal with the pulse width modulation voltage being greater than the voltage reference;
- a pulse width modulation controller to derive a clock signal from the differential data signal free of timing pulses;
- and
- a current mode logic pad to receive an input signal and a current mode logic to CMOS converter to produce the differential data signal from the input signal.
3 more elements
A pulse-width demodulator, comprising:
- an even path decoder core receiving a differential input signal and outputting a demodulated, even data signal, wherein the even path decoder core includes:
- a first integrator leg to charge to a voltage reference in response to receipt of the differential input signal;
- a second integrator leg to charge to a charge level with a first signal of the differential data signal being at a first level and output a pulse width modulation even voltage, the charge level being based on an amount of time in which the first signal is at the first level;
- a comparator to receive the voltage reference and the pulse width modulation voltage and to output a low output signal with the pulse width modulation even voltage being less than the voltage reference and output a high output signal with the pulse width modulation even voltage being greater than the voltage reference;
- an odd path decoder core receiving the differential input signal and outputting a demodulated, odd data signal, wherein the odd path decoder core includes:
- a third integrator leg to charge to the voltage reference in response to receipt of the differential input signal;
- a fourth integrator leg to charge to another charge level with the second signal of the differential data signal being at a first level and output a pulse width modulation odd signal the another charge level being based on another amount of time in which the second signal is at the first level;
- a comparator to receive the voltage reference and the pulse width modulation odd voltage and to output a low output signal with the pulse width modulation odd voltage being less than the voltage reference and output a high output signal with the pulse width modulation odd voltage being greater than the voltage reference;
- a pulse width modulator controller receiving the differential signal and outputting a clock signal;
- and
- a sampling and retiming circuitry receiving the clock signal, the even data signal, and the odd data signal to output a half rate even data signal and a half rate odd data signal.
8 more elements
A method for demodulating a pulse width modulated signal, comprising:
- receiving the pulse width modulation signal, the pulse width modulation signal having first and second levels, wherein the pulse width modulation signal is a differential signal with a positive signal and a negative signal;
- charging, by a first current source, a first capacitor in response to the pulse width modulation signal changing from the first level to the second level during a first time interval;
- charging, by a second current source, a second capacitor in response to the negative signal changing from the first level to a third level during the first time interval;
- and
- demodulating the pulse width modulation signal for the first time interval based on voltages of the first capacitor and the second capacitor with a comparator outputting a low negative signal when the voltage at the second capacitor being less than the voltage at the first capacitor and outputting a high negative output with the voltage at the second capacitor being greater than the voltage at the first capacitor.
2 more elements
Dependencies are inferred from the claim text.