Scalable, stackable, and BEOL-process compatible integrated neuron circuit

A method of manufacturing an integrated neuron circuit structure, the method comprising:

• forming first and second voltage supply leads out of a first metal layer on a top surface of an integrated circuit wafer;
• forming a first dielectric layer on portions of the top surface of the wafer not covered by said first metal layer;
• forming first and second negative differential resistance material regions on portions of said first and second voltage supply leads;
• forming a second dielectric layer on portions of the top surface of the wafer not covered by said first and second negative differential resistance material regions;
• forming first and second intermediate node lines out of a second metal layer on said first and second negative differential resistance material regions and on said second dielectric layer;
• forming a third dielectric layer on portions of the top surface of the wafer not covered by said first and second intermediate node lines;
• forming a dielectric thin film on the top surface of the wafer;
• patterning said dielectric thin film and forming a first lower capacitor plate and a first resistor line out of a first metal thin-film on portions of the first intermediate node line and on portions of the thin film dielectric layer, and forming a second lower capacitor plate and a second resistor line out of said first metal thin-film on portions of the second intermediate node line and on portions of the thin-film dielectric layer, the second resistor line contacting the first and second intermediate node lines;
• covering the first and second lower capacitor plates with a capacitor dielectric layer;
• covering portions of the capacitor dielectric layer with first and second upper capacitor plates formed out of a second metal thin-film layer;
• forming a fourth dielectric layer on the top surface of the wafer;
• forming through the fourth dielectric layer via connections to the first and second upper capacitor plates;
• to a portion of the second resistor line above the second connection line and to a portion of the first resistor line not above the first connection line;
• the via connections being made out a third metal layer.