Application processor that performs core switching based on modem data and a system on chip (SOC) that incorporates the application processor

A system on chip (SoC) comprising:

• an application processor comprising:
• a first processor core that processes a first amount of data per unit time, and
• a second processor core that processes a second amount of data per unit time, which is larger than the first amount of data;
• a communications processor that wirelessly receives a message signal via an antenna from an external device and determines a size of a data packet within the message signal;
• and
• a power management integrated circuit (IC) that supplies power to the communications processor, wherein
• the application processor activates the first processor core or the second processor core based on at least one of an amount of the power supplied to the communications processor by the power management IC and the size of the data packet
• wherein the amount of power supplied to the communications processor by the power management IC is indicated by an amount of current supplied to the communications processor by the power management IC
• wherein the amount of power supplied to the communications processor by the power management IC is indicated by an amount of current supplied to the communications processor by the power management IC.

A computer program stored on a non-transitory computer-readable medium for execution by an application processor of a system on chip (SoC) to activate a first processor core or a second processor core of the application processor, the first processor core processing a first amount of data per unit time, the second processor core processing a second amount of data per unit time, which is larger than the first amount of data, and the application processor being in communication with a communications processor of the SoC that wirelessly receives a data packet within a message signal via an antenna, the computer program comprising instructions that:

• activate the first processor core or the second processor core based on at least one of an amount of power supplied to the communications processor by a power management integrated circuit (IC) of the SoC and a size of the data packet
• wherein the power supplied to the communications processor is indicated by an amount of current supplied to the communications processor,
• wherein the application processor activates:
• the first processor core in response to determining the amount of current supplied to the communications processor is equal to a first magnitude, and
• the second processor core in response to determining the amount of the current supplied to the communications processor is equal to a second magnitude that is larger than the first magnitude.