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US 10,897,384 B2Granted
HART FSK digital demodulator
AssigneeTexas Instruments Incorporated
InventorsMichael Douglas Snedeker, Hugo Cheung
Life of this patent
Estimating the term…
Abstract
A digital demodulator for use with a Highway Addressable Remote Transducer (HART) modem is provided. Analog input signals are digitized according to a sampling clock rate to produce a discrete time signal. Filtering and edge detection allow determinations of “mark” or “space” data in a demodulated signal in conjunction with analyzing a detected signal period, a cycle period, count histories and/or an on/off signal period.
Claims20
A digital demodulator comprising:
- level crossing detection circuitry having an input and an output;
- digital synchronization circuitry having an input coupled to the output of the level crossing detection circuitry and having an output;
- a digital glitch filter having an input coupled to the output of the digital synchronization circuitry and having an output;
- edge detection circuitry having an input coupled to the output of the digital glitch filter and having an output;
- a decision module to determine digital data from demodulated signals, including:
- a count circuit to count time between similar edges of a discrete time signal, having an input coupled to the output of the edge detection circuitry and having an output;
- a store counts circuit to store count time history information, having an input coupled to the output of the count circuit and having an output;
- and
- a decide circuit to determine the digital data based at least in part on the stored count time history information, having an input coupled to the output of the store counts circuit.
6 more elements
A method of digital demodulation comprising:
- detecting a signal transition;
- sampling a detected analog signal at a clock rate to produce a discrete time signal;
- filtering the discrete time signal;
- detecting a plurality of transitioning edges of the discrete time signal;
- determining a transition time period between similar transitioning edges of the discrete time signal;
- storing transition time period information;
- and
- determining digital bit data based at least in part on the stored transition time period information.
5 more elements
A digital demodulator adapted to:
- detect a signal transition;
- sample a detected analog signal, according to a clock rate, to generate a discrete time signal;
- filter the discrete time signal;
- detect a transitioning edge of the discrete time signal;
- determine a count time between similar edge transitions of the discrete time signal;
- store count time history information;
- and
- determine digital bit data based at least in part on the stored count time history information.
5 more elements
A system comprising a digital demodulator wherein the digital demodulator includes:
- level crossing circuitry having an input and an output, operable to determine a level crossing in connection with comparing an input signal level to a reference level;
- digital synchronization circuitry having an input coupled to the output of the level crossing circuitry and having an output, operable to synchronize a continuous analog input signal with a clocked sampling signal to produce a discrete time signal;
- a digital glitch filter having an input coupled to the output of the digital synchronization circuitry and having an output;
- edge detection circuitry having an input coupled to the output of the digital glitch filter and having an output, operable to determine a rising-to-rising edge or a falling-to-falling edge of the discrete time signal;
- a decision module to determine digital data from demodulated signals, including:
- a count circuit to count time between similar edges of the discrete time signal, having an input coupled to the output of the edge detection circuitry and having an output;
- a store counts circuit to store count time history information, having an input coupled to the output of the count circuit and having an output;
- and
- a decide circuit to determine the digital data based at least in part on the stored count time history information, having an input coupled to the output of the store counts circuit.
6 more elements
Dependencies are inferred from the claim text.