US 10,897,332 B2Granted

Method and device for transmitting synchronization signal blocks

AssigneeGuangdong Oppo Mobile Telecommunications Corp., Ltd.

InventorsNing Yang, Zhi Zhang

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Abstract

The present application provides a method and apparatus for transmitting synchronization signal blocks, the method comprising: determining M target frequency domain locations for carrying M synchronization signal blocks within a broadband component carrier, where each of the target frequency domain locations is used for carrying one synchronization signal block, and M is a positive integer greater than or equal to 1; transmitting the M synchronization signal blocks to a terminal device on the M target frequency domain locations. The method for transmitting the synchronization signal blocks provided by the present application can implement transmission of multiple synchronization signal blocks within a broadband component carrier, thus meeting the requirements of new radio communication system.

Claims17

Dependent claims

A method for transmitting synchronization signal blocks, comprising:

when target synchronization signal blocks in S synchronization signal blocks are received within a broadband component carrier, determining, according to target frequency domain locations carrying the target synchronization signal blocks, other target frequency domain locations for carrying other synchronization signal blocks in S target frequency domain locations, wherein the other synchronization signal blocks are part or all of synchronization signal blocks except the target synchronization signal blocks in the S synchronization signal blocks, and the other target frequency domain locations are part or all of target frequency domain locations except target frequency domain locations carrying the target synchronization signal blocks in the S target frequency domain locations, and each of the target frequency domain locations is used for carrying one synchronization signal block;
wherein a frequency interval between two adjacent target frequency domain locations in the S target frequency domain locations is a first target frequency interval;
wherein the determining, according to target frequency domain locations carrying the target synchronization signal blocks, other target frequency domain locations for carrying other synchronization signal blocks in S target frequency domain locations comprises:
determining, according to the target frequency domain locations carrying the target synchronization signal blocks and the first target frequency interval, the other target frequency domain locations;
wherein the first target frequency interval is an integer multiple of a synchronization signal frequency grid;
wherein the S target frequency domain locations are determined based on N second frequency domain locations, and a frequency interval between two adjacent second frequency domain locations in the N second frequency domain locations is a second target frequency interval, wherein N is a positive integer greater than or equal to S.

3 more elements

A terminal device, comprising a processor and a memory storing instructions thereon, the processor when executing the instructions, being configured to:

control the transceiver to receive synchronization signal blocks within a broadband component carrier;
when target synchronization signal blocks in S synchronization signal blocks are received within the broadband component carrier, determine, according to target frequency domain locations carrying the target synchronization signal blocks, other target frequency domain locations for carrying other synchronization signal blocks in S target frequency domain locations, wherein the other synchronization signal blocks are part or all of synchronization signal blocks except the target synchronization signal blocks in the S synchronization signal blocks, and the other target frequency domain locations are part or all of target frequency domain locations except target frequency domain locations carrying the target synchronization signal blocks in the S target frequency domain locations, and each of the target frequency domain locations is used for carrying one synchronization signal block;
wherein a frequency interval between two adjacent target frequency domain locations in the S target frequency domain locations is a first target frequency interval;
wherein the processor is specifically configured to:
determine, according to the target frequency domain locations carrying the target synchronization signal blocks and the first target frequency interval, the other target frequency domain locations;
wherein the first target frequency interval is an integer multiple of a synchronization signal frequency grid;
wherein the S target frequency domain locations are determined based on N second frequency domain locations, and a frequency interval between two adjacent second frequency domain locations in the N second frequency domain locations is a second target frequency interval, wherein N is a positive integer greater than or equal to S.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/364,755Filed 26 Mar 2019 · continuation
Priority: WO PCT/CN2017/1096056 Nov 2017
Published: US 2019/0222368 A118 Jul 2019
Granted: 19 Jan 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H04L 5/001
The frequencies being orthogonal, e.g. OFDM or DMT: the frequencies being arranged in component carriers
H04L 5/0048
Arrangements for allocating sub-channels of the transmission path: allocation of pilot signals, i.e. of signals known to the receiver
H04L 5/0053
Arrangements for allocating sub-channels of the transmission path: allocation of signalling, i.e. of overhead other than pilot signals
H04L 5/0094
Signalling for the administration of the divided path, e.g. signalling of configuration information: indication of how sub-channels of the path…