US 10,897,263 B1 · Multiple paths bootstrap configuration for sample and hold circuit

Abstract

A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network periodically transitioning between a holding phase and a tracking phase. The bootstrap switching network includes a primary bootstrap path that drives only one load: the gate terminal of the sampling transistor. One or more auxiliary bootstrap paths drive other transistors in the bootstrap switching network. This absolutely minimizes the parasitic capacitance due to fan-out on the primary bootstrap path. Additionally, the provision of two (or more) bootstrap capacitors allows bulk terminals of transistors on the primary bootstrap path to be connected to an auxiliary bootstrap path, further reducing parasitic capacitance on the primary bootstrap path. Additional auxiliary bootstrap paths may be added, providing the opportunity to optimize each clock driver to a specific driven transistor. Additional bootstrap capacitors may be added, to distribute the capacitance among auxiliary bootstrap paths. The reduction in parasitic capacitance at the sampling transistor enhances its linearity, and hence accuracy, at very high frequencies.

Claims20

Dependent claims

A multipath bootstrapped sampling circuit for an analog to digital converter receiving a supply voltage and periodic clock signal, having a ground, sampling an analog input signal voltage, and outputting a sampled voltage value, the sampling circuit comprising:

a sampling capacitor;
a sampling transistor interposed between the sampling capacitor and the analog input signal voltage;
first and second bootstrap capacitors;
and
a bootstrap switching network configured to periodically transition between a holding phase and a tracking phase in response to the periodic clock signal, and further configured to:
in the holding phase, charge the bootstrap capacitors to the supply voltage by connecting them between the supply voltage and ground, and isolate the sampling capacitor by applying ground to a gate terminal of the sampling transistor;
and
in the tracking phase, disconnect the bootstrap capacitors from the supply voltage and apply a sum of the first capacitor voltage and analog input signal voltage to the gate terminal of the sampling transistor, thereby connecting the sampling capacitor to the analog input voltage;
wherein the bootstrap switching network comprises
a primary bootstrap path connected to the first bootstrap capacitor and driving only the gate terminal of the sampling transistor;
and
at least a first auxiliary bootstrap path driving gate terminals of one or more other transistors in the bootstrap switching network.

9 more elements

A method of repeatedly sampling an input signal voltage by a multipath bootstrapped sampling circuit for an analog to digital converter, the sampling circuit receiving a supply voltage and periodic clock signal, having a ground, and outputting a sampled voltage value, the sampling circuit comprising a sampling capacitor, a sampling transistor interposed between the sampling capacitor and an analog input signal voltage, first and second bootstrap capacitors, and a bootstrap switching network comprising a primary bootstrap path and at least a first auxiliary bootstrap path, the method comprising:

in a holding phase of the bootstrap switching network, charging the first and second bootstrap capacitors to the supply voltage by connecting them between the supply voltage and ground, and applying ground to a gate terminal of the sampling transistor by the primary bootstrap path;
and
in a tracking phase of the bootstrap switching network, disconnecting the first and second bootstrap capacitors from the supply voltage and applying a sum of a voltage on the first bootstrap capacitor and the analog input signal voltage to the gate terminal of the sampling transistor by the primary bootstrap path;
wherein the primary bootstrap path drives only the gate terminal of the sampling transistor, and the first auxiliary bootstrap path drives the gate terminals of one or more other transistors in the bootstrap switching network.

1 more element

A wireless communication apparatus, comprising:

processing circuitry;
and
communication circuitry operatively connected to the processing circuitry and including one or more Analog to Digital Converters, at least one of which includes one or more multipath bootstrapped sampling circuits;
wherein each multipath bootstrapped sampling circuit receives a supply voltage and periodic clock signal and has a ground, and each multipath bootstrapped sampling circuit samples an analog input signal voltage and outputs a sampled voltage value;
and
wherein each multipath bootstrapped sampling circuit comprises
a sampling capacitor;
a sampling transistor interposed between the sampling capacitor and the analog input signal voltage;
first and second bootstrap capacitors;
and
a bootstrap switching network configured to periodically transition between a holding phase and a tracking phase in response to the periodic clock signal, and further configured to:
in the holding phase, charge the bootstrap capacitors to the supply voltage by connecting them between the supply voltage and ground, and isolate the sampling capacitor by applying ground to a gate terminal of the sampling transistor;
and
in the tracking phase, disconnect the bootstrap capacitors from the supply voltage and apply a sum of the first capacitor voltage and analog input signal voltage to the gate terminal of the sampling transistor, thereby connecting the sampling capacitor to the analog input voltage;
wherein the bootstrap switching network comprises
a primary bootstrap path connected to the first bootstrap capacitor and driving only the gate terminal of the sampling transistor;
and
at least a first auxiliary bootstrap path driving gate terminals of one or more other transistors in the bootstrap switching network.

15 more elements

Dependencies are inferred from the claim text.

Multiple paths bootstrap configuration for sample and hold circuit

Life of this patent

Multiple paths bootstrap configuration for sample and hold circuit

Life of this patent

Abstract

Claims20