Systems and methods for performing phase error correction

A system for performing phase error correction, the system comprising:

• a phase detector circuitry configured to:
• receive a reference clock signal;
• receive a target clock signal output from feedback divider circuitry;
• generate, at a first clock cycle of the reference clock signal subsequent to the receiving, a first value based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal;
• output the generated first value to the feedback divider circuitry;
• the feedback divider circuitry configured to:
• set a phase adjustment variable to be a first division value equal to zero during the first clock cycle;
• receive the generated first value from the phase detector circuitry;
• set the phase adjustment variable to be a second division value based on the first value during a second clock cycle;
• adjust, at the second clock cycle of the reference clock signal immediately next to the first clock cycle, a phase of the target clock signal a first time based on the phase adjustment variable;
• output the target clock signal with the adjusted phase to an input of the phase detector circuitry;
• and
• set the phase adjustment variable to be the first division value equal to zero during a third clock cycle;
• the phase detector circuitry further configured to:
• receive, from the feedback divider circuitry, the target clock signal with the phase adjusted based on the given amount computed using the first value;
• at the third clock cycle of the reference clock signal immediately next to the second clock cycle, generate a second value based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal;
• and
• the feedback divider circuitry, further configured to:
• set the phase adjustment variable to be a third division value based on the first value, the second value, and the second division value during a fourth clock cycle;
• and
• adjust, at the fourth clock cycle of the reference clock signal immediately next to the third clock cycle, the phase of the target clock signal a second time based on the phase adjustment variable.