Phase locked circuit, method of operating the same, and transceiver

A phase locked circuit comprising:

• an oscillator configured to generate an output clock signal;
• a first phase difference detector configured to output a first voltage that indicates a phase difference between an input clock signal and a feedback clock signal;
• a phase lock detector configured to detect whether a level of the first voltage is included in a previously set voltage level period to output a first detection signal;
• a charge pump controller configured to output a charge pump control signal that controls an amount of output current of the charge pump based on the first detection signal;
• and
• a second phase difference detector configured to output a second detection signal that indicates the phase difference between the input clock signal and the feedback clock signal;
• wherein the charge pump is configured to output the output current based on the second detection signal and the charge pump control signal, and
• wherein a frequency of the output clock signal is based on the amount of the output current, and the feedback clock signal is based on the output clock signal.

A method of operating a phase locked circuit, the method comprising:

• detecting, by a first phase difference detector, a phase difference between an input clock signal and a feedback clock signal;
• outputting a logic high upper limit detection signal when the phase difference indicates a phase of the feedback clock signal is later than a target phase and outputting a logic high lower limit detection signal when the phase difference indicates the phase of the feedback clock signal is earlier than the target phase;
• controlling an output current of a charge pump connected to a second phase difference detector based on the lower limit detection signal and the upper limit detection signal;
• and
• controlling a frequency of an output clock signal based on the output current.