Back to results
US 10,897,253 B2Granted
Calibration circuit and calibration apparatus including the same
AssigneeSK hynix Inc.
InventorsOung Sic Cho, Jong Hoon Oh
Life of this patent
Estimating the term…
Abstract
A system may include: a first memory device; a second memory device; a third memory device; and a fourth memory device, wherein the first memory device to the fourth memory device are configured to share a resistor for impedance matching, wherein the first memory device to the fourth memory device are coupled to have a chain shape, wherein the forth memory device generates a completion signal when performance is completed and the first memory device receives the completion signal provided from the fourth memory device.
Claims20
A system comprising:
- a first non-volatile memory device;
- a second non-volatile memory device;
- a third non-volatile memory device;
- and
- a fourth non-volatile memory device,
- wherein the first non-volatile memory device to the fourth non-volatile memory device are configured to share a resistor for impedance matching,
- wherein the first non-volatile memory device to the fourth non-volatile memory device are coupled to have a chain shape,
- wherein the fourth non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the fourth non-volatile memory device.
5 more elements
A system comprising:
- a first non-volatile memory device to an eighth non-volatile memory device,
- wherein the first non-volatile memory device to the eighth non-volatile memory device are configured to share a resistor for impedance matching,
- wherein first non-volatile memory device to the eighth non-volatile memory device are coupled to have a chain shape,
- wherein the eighth non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the eighth non-volatile memory device.
1 more element
A system comprising:
- a first non-volatile memory device to an sixteenth non-volatile memory device,
- wherein the first non-volatile memory device to the sixteenth non-volatile memory device are configured to share a resistor for impedance matching,
- wherein the first non-volatile memory device to the sixteenth non-volatile memory device are coupled to have a chain shape,
- wherein the sixteenth non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the sixteenth non-volatile memory device.
1 more element
A system comprising:
- a first non-volatile memory device to a thirty-second non-volatile memory device,
- wherein the first non-volatile memory device to the thirty-second non-volatile memory device are configured to share a resistor for impedance matching,
- wherein the first non-volatile memory device to the thirty-second non-volatile memory device are coupled to have a chain shape,
- wherein the thirty-second non-volatile memory device generates a completion signal when performance is completed and the first non-volatile memory device receives the completion signal provided from the thirty-second non-volatile memory device.
1 more element
A system comprising:
- a first non-volatile memory device;
- a second non-volatile memory device;
- a third non-volatile memory device;
- and
- a fourth non-volatile memory device,
- wherein the first non-volatile memory device to the fourth non-volatile memory device are configured to share a resistor for impedance matching,
- wherein the first non-volatile memory device to the fourth non-volatile memory device are coupled to have a chain shape,
- wherein at least one of the first non-volatile memory device to the fourth non-volatile memory device includes a volatile memory.
5 more elements
Dependencies are inferred from the claim text.