Radio frequency switching circuitry with reduced switching time

Radio frequency (RF) switching circuitry comprising:

• an input node, an output node, and a gate drive node;
• a plurality of field-effect transistors (FETs) coupled between the input node, the output node, and the gate drive node such that a gate contact of each one of the plurality of FETs is coupled to the gate drive node via a common resistor, wherein the plurality of FETs is configured to:
• turn on and provide a low impedance path between the input node and the output node when a gate drive signal at the gate drive node is provided at a positive power supply voltage;
• and
• turn off and provide a high impedance path between the input node and the output node when the gate drive signal is provided at a negative power supply voltage, wherein the high impedance path has a higher impedance than the low impedance path;
• and
• switch acceleration circuitry comprising:
• a bypass FET configured to selectively bypass the common resistor in response to a multi-level drive signal;
• acceleration control signal generator circuitry configured to receive a digital switching control signal and provide a delayed digital switching control signal and a digital acceleration control signal, wherein the delayed digital switching control signal is used to generate the gate drive signal and the digital acceleration control signal is used to generate the multi-level drive signal;
• and
• multi-level driver circuitry configured to use a built-in gate capacitance of the bypass FET in order to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage, wherein the multi-level driver circuitry comprises a multi-level driver diode having a cathode coupled to a gate of the bypass FET to maintain charge stored by the built-in gate capacitance of the bypass FET, wherein the multi-level driver circuitry comprises:
• a first sub-driver configured to receive the acceleration control signal and provide one of the positive power supply voltage and the negative power supply voltage at a first sub-driver output node;
• a second sub-driver configured to receive the delayed switching control signal and provide one of a ground and the negative power supply voltage at a second sub-driver output node;
• a first multi-level driver FET coupled between a positive power supply voltage node, an anode of the multi-level driver diode, and the first sub-driver output node and configured to selectively provide a low impedance path between the positive power supply voltage node and the anode of the multi-level driver diode when the negative power supply voltage is provided at the first sub-driver output node and provide a high impedance path between the positive power supply voltage node and the anode of the multi-level driver diode when the positive power supply voltage is provided at the first sub-driver output node;
• a multi-level drive signal output node coupled to a cathode of the multi-level driver diode;
• and
• a second multi-level driver FET coupled between the multi-level drive signal output node, the second sub-driver output node, and the first sub-driver output node and configured to selectively provide a low impedance path between the multi-level drive signal output node and the second sub-driver output node when the positive power supply voltage is provided at the first sub-driver output node and provide a high impedance path between the multi-level drive signal output node and the second sub-driver output node when the negative power supply voltage is provided at the first sub-driver output node.