Frequency demultiplication adjustment method of PLL

A frequency demultiplication adjustment method of a phase-locked loop (PLL), applied to an embedded system, providing a phase-locked loop, a processor and a processor frequency adjustor;

• wherein the method comprises following steps of:
• Step S1, obtaining a plurality of corresponding frequency demultiplication frequency points according to a default frequency demultiplication value of the phase-locked loop;
• Step S2, obtaining a load state of the processor within a predetermined sampling period, and obtaining a target frequency point of the processor according to the load state by the processor frequency adjustor;
• Step S3, determining a frequency range of a virtual frequency point to be added according to the position of the target frequency point between the frequency points;
• Step S4, performing calculation within the frequency range to obtain equivalent frequencies corresponding to a plurality of virtual frequency points;
• Step S5, judging whether the frequency of the target frequency point is equal to the equivalent frequency corresponding to one of the virtual frequency points;
• if not, switching the processor frequency adjustor to the corresponding frequency demultiplication frequency point;
• and
• Step S6, adjusting the frequency demultiplication value of the phase-locked loop, so that the phase-locked loop outputs a clock source signal corresponding to the virtual frequency points to the processor.