A multi-level capacitive digital-to-analog converter, comprising:
- at least one capacitor switch circuit having a first reference input terminal to apply a first reference potential and a second reference input terminal to apply a second reference potential, wherein the at least one capacitor switch circuit comprises:
- a differential operational amplifier having a first input node and a second input node,
- a first current path and a second current path, the first current path being coupled to the first reference input terminal and the second current path being coupled to the second reference input terminal,
- wherein the first input node of the differential operational amplifier is connected to the first current path and the second input node of the differential operational amplifier is connected to the second current path,
- a first controllable switch being arranged between the second input node of the differential operational amplifier and the first current path,
- a second controllable switch being arranged between the first input node of the differential operational amplifier and the second current path,
- a first integrating capacitor and a second integrating capacitor,
- a first transfer capacitor and a second transfer capacitor,
- wherein the first transfer capacitor is arranged in the first current path between the first reference input terminal and the first integrating capacitor, and
- wherein the second transfer capacitor is arranged in the second current path between the second reference input terminal and the second integrating capacitor,
- a third controllable switch and a fourth controllable switch,
- wherein the third controllable switch is arranged in the first current path between the first integrating capacitor and the first transfer capacitor, and
- wherein the fourth controllable switch is arranged in the second current path between the second integrating capacitor and the second transfer capacitor, a fifth and a sixth controllable switch,
- wherein the fifth controllable switch is arranged between a third reference potential and a first position of the first current path, said first position of the first current path being located between the third controllable switch and the first transfer capacitor,
- wherein the sixth controllable switch is arranged between the third reference potential and a first position of the second current path, said first position of the second current path being located between the fourth controllable switch and the second transfer capacitor,
- wherein the first controllable switch is arranged between the second input node of the differential operational amplifier and the first position of the first current path, and
- wherein the second controllable switch is arranged between the first input node of the differential operational amplifier and the first position of the second current path,
- a seventh controllable switch being arranged in the first current path between the first reference input terminal and the first transfer capacitor,
- an eighth controllable switch being arranged in the second current path between the second reference input terminal and the second transfer capacitor,
- a ninth controllable switch being arranged between the second reference input terminal and a second position of the first current path, said second position of the first current path being located between the seventh controllable switch and the first transfer capacitor,
- a tenth controllable switch being arranged between the first reference input terminal and a second position of the second current path, said second position of the second current path being located between the eighth controllable switch and the second transfer capacitor,
- an eleventh controllable switch being arranged between the third reference potential and the second position of the first current path, and
- a twelfth controllable switch being arranged between the third reference potential and the second position of the second current path.