Bias circuit and amplification apparatus

An amplification apparatus comprising:

• a bias circuit for supplying a bias voltage;
• and
• an amplification circuit to which the bias voltage is configured to be supplied from the bias circuit, the bias circuit comprising:
• a first voltage outputting unit comprising:
• a first current source configured to increase and decrease a first output current depending on the bias voltage;
• and
• a first voltage dropping portion including a first transistor which is a MOSFET with a first polarity and through which the first output current from the first current source flows as a drain current,
• the first voltage outputting unit being configured to output a first output voltage from a connection point between the first current source and the first voltage dropping portion;
• a second voltage outputting unit comprising:
• a second current source configured to output a constant current as a second output current;
• and
• a second voltage dropping portion including a second transistor which is a MOSFET with a second polarity different from the first polarity and through which the second output current from the second current source flows as a drain current,
• the second voltage outputting unit being configured to output a second output voltage from a connection point between the second current source and the second voltage dropping portion;
• and
• a voltage comparator configured to output the bias voltage, and increase and decrease the bias voltage such that the first and second output voltages become equal, based on a difference between the first and second output voltages,
• the amplification circuit comprising:
• a source follower stage comprising:
• a third current source configured to increase and decrease a third output current depending on the bias voltage;
• and
• a third transistor which is a MOSFET with the first polarity and has a gate to which an input signal is configured to be inputted, the third output current from the third current source being configured to flow as a drain current through the third transistor;
• and
• an amplification stage comprising a fourth transistor which is a MOSFET with the second polarity and has a gate to which an output of the source follower stage is configured to be inputted, the amplification stage being configured to amplify the output of the source follower stage.