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US 10,897,132 B2Granted
Electrostatic discharge protection circuit and design
AssigneeWestern Digital Technologies, Inc.
InventorsBhawna Tomar, Rohith Aravind Mahale, Seema Malhotra, Ajay Kanth Chitturi
Life of this patent
Estimating the term…
Abstract
Electrostatic discharge (ESD) protection for an electronic circuit includes a timer circuit that controls multiple clamp circuits. In this way, less circuit area may be used for the timer circuit as compared to conventional ESD protection schemes. In some embodiments, the ESD protection circuit is employed in a data storage apparatus that includes a non-volatile memory array (e.g., NAND devices).
Claims20
An electrostatic discharge protection circuit, comprising:
- a first clamp circuit directly coupled to an external signal path;
- a second clamp circuit directly coupled to the external signal path;
- a first driver circuit coupled to the first clamp circuit to turn on the first clamp circuit in response to an electrostatic discharge event on the external signal path;
- a second driver circuit coupled to the second clamp circuit to turn on the second clamp circuit in response to the electrostatic discharge event;
- and
- a first timer circuit coupled to the first driver circuit and the second driver circuit to turn off the first clamp circuit and the second clamp circuit after a delay period following the electrostatic discharge event.
3 more elements
An electrostatic discharge protection circuit, comprising:
- a plurality of means for clamping, wherein each of the plurality of means for clamping is directly coupled to a same external signal path;
- a plurality of means for turning on the plurality of means for clamping in response to an electrostatic discharge event on the same external signal path;
- and
- a means for turning off the plurality of means for clamping after a delay period following the electrostatic discharge event.
1 more element
A circuit design method, comprising:
- receiving information for a timer circuit for electrostatic discharge protection, a plurality of clamp circuits for the electrostatic discharge protection, and a plurality of driver circuits for the electrostatic discharge protection;
- determining a location of the timer circuit within a circuit layout;
- determining locations of the plurality of clamp circuits within the circuit layout, wherein each of the plurality of clamp circuits is directly coupled to a same external signal path;
- determining locations of the plurality of driver circuits within the circuit layout;
- routing at least one signal trace between the timer circuit and the plurality of driver circuits within the circuit layout;
- routing a plurality of signal traces between the plurality of driver circuits and the plurality of clamp circuits within the circuit layout such that each of the plurality of driver circuits turns on a respective one of the plurality of clamp circuits in response to an electrostatic discharge event on the same external signal path;
- generating a digital representation of the circuit layout;
- and
- storing the digital representation of the circuit layout.
6 more elements
Dependencies are inferred from the claim text.