Magnetic memory device and method for manufacturing the same

A magnetic memory device, comprising:

• a substrate including a cell region and a peripheral circuit region;
• a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate;
• a lower interconnection structure in the first interlayer insulating layer;
• a second interlayer insulating layer and a third interlayer insulating layer sequentially stacked on the first interlayer insulating layer;
• a peripheral conductive line in the second interlayer insulating layer on the peripheral circuit region, the third interlayer insulating layer covering a top surface of the peripheral conductive line;
• a bottom electrode contact penetrating the second interlayer insulating layer and the third interlayer insulating layer on the cell region, the bottom electrode contact having a top surface located at the same height as or a higher height than a top surface of the third interlayer insulating layer;
• a data storage pattern on the top surface of the bottom electrode contact;
• and
• a capping insulating layer covering a sidewall of the data storage pattern and extending from the sidewall of the data storage pattern in the cell region onto the peripheral circuit region along the top surface of the third interlayer insulating layer.

A magnetic memory device, comprising:

• a substrate including a cell region and a peripheral circuit region;
• a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate;
• a second interlayer insulating layer and a protective insulating layer sequentially stacked on the first interlayer insulating layer;
• a third interlayer insulating layer on the protective insulating layer;
• interconnection lines in the first interlayer insulating layer;
• a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines;
• a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines;
• and
• a data storage pattern on the bottom electrode contact,
• wherein:
• the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact,
• the bottom electrode contact penetrates the second interlayer insulating layer and the protective insulating layer,
• the peripheral conductive line and the peripheral conductive contact are in the second interlayer insulating layer,
• the protective insulating layer covers a top surface of the peripheral conductive line,
• the bottom electrode contact penetrates the third interlayer insulating layer,
• the third insulating layer has a top surface at an interface with a layer of a different material,
• the top surface of the bottom electrode contact is located at the same height as or a higher height than the top surface of the third interlayer insulating layer,
• the third interlayer insulating layer extends from the cell region onto the peripheral circuit region along a top surface of the protective insulating layer, and
• a height of the top surface of the third interlayer insulating layer on the peripheral circuit region is lower than a height of the top surface of the third interlayer insulating layer on the cell region.