Manufacturing method of an HEMT transistor of the normally off type with reduced resistance in the on state and HEMT transistor
AssigneeSTMicroelectronics S.r.l.
InventorFerdinando Iucolano
Life of this patent
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Abstract
A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.
Claims17
A method of manufacturing a high electron mobility transistor (HEMT), comprising:
- forming a semiconductor heterostructure;
- forming a first gate layer of semiconductor material on the heterostructure;
- forming a second gate layer, containing dopant impurities of a P type, on the first gate layer;
- removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region;
- and
- thermally annealing the doped gate region so as to cause diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as a lateral distance from the doped gate region increases;
- wherein a thickness of the first gate layer, a concentration of dopant impurities of the P type of the second gate layer, and the thermal annealing are configured to produce:
- a concentration of dopant impurities of the P type of the doped gate region comprised between 1018 cm−3 and 5×1019 cm−3;
- a concentration of dopant impurities of the P type, in an interface between the heterostructure and the first gate layer that is aligned with the doped gate region, comprised between 1018 cm−3 and 1019 cm−3;
- and a concentration of dopant impurities of the P type in portions of the heterostructure laterally displaced with respect to the doped gate region by 20 nm, of less than 1017 cm−3.
A method comprising:
- manufacturing a high electron mobility transistor (HEMT), the manufacturing including:
- forming a semiconductor heterostructure;
- epitaxially forming a first gate layer of intrinsic semiconductor material on the heterostructure;
- epitaxially forming a second gate layer of doped semiconductor material on the first gate layer;
- forming a first doped gated region by removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form the first doped gate region;
- and
- perform a thermal annealing, after forming the first doped gate region, the thermal annealing causing dopant impurities from the first doped gate region to diffuse in the first gate layer and in the heterostructure;
- wherein forming the semiconductor heterostructure comprises:
- forming a channel layer;
- and
- forming a barrier layer on the channel layer, wherein forming the channel layer and the barrier layer include forming layers of respective compound materials that include elements of groups III-V, wherein the intrinsic semiconductor material of the first gate layer is a different semiconductor material than the barrier layer.
A method of manufacturing a high electron mobility transistor (HEMT), comprising:
- forming a semiconductor heterostructure that includes a channel layer and a barrier layer on the channel layer, wherein the channel layer and the barrier layer are layers of respective compound materials that include elements of groups III-V;
- forming a first gate layer of semiconductor material directly on the barrier layer of the heterostructure, the semiconductor material of the first gate layer being a different material than the compound material of the barrier layer;
- forming a second gate layer, containing P-type dopant impurities, on the first gate layer;
- removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region;
- and
- thermally annealing the doped gate region so as to cause diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as a lateral distance from the doped gate region increases;
- forming a buffer layer on a semiconductor substrate and below the heterostructure, wherein the buffer layer has a thickness 20 comprised between 1 μm and 8 μm.
Dependencies are inferred from the claim text.