Back to results
US 10,896,966 B2Granted
Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-jin Lee, Bong-soo Kim, Ji-young Kim, Ho-rim Yoo
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate including a first region and a second region, a buried gate structure located on a first recess in the first region of the substrate, and a recess gate structure located on a second recess in the second region of the substrate, wherein the buried gate structure is buried in the substrate, an upper portion of the recess gate structure is not buried in the substrate, and a first work function adjustment layer in the buried gate structure may include a material identical to a material included in a second work function layer of the recess gate structure.
Claims16
A semiconductor device comprising:
- a substrate comprising a first region and a second region;
- a buried gate structure located on a first recess in the first region of the substrate and comprising a first work function adjustment layer;
- and
- a recess gate structure located on a second recess in the second region of the substrate and comprising a second work function adjustment layer,
- wherein the buried gate structure is buried in the substrate,
- wherein an upper portion of the recess gate structure is not buried in the substrate,
- wherein the first work function adjustment layer in the buried gate structure and the second work function adjustment layer in the recess gate structure comprise the same material, and
- wherein a depth of the first recess is greater than a depth of the second recess.
5 more elements
A semiconductor device comprising:
- a substrate comprising a first region and a second region;
- a buried gate structure on a first recess in the first region of the substrate;
- and
- a recess gate structure on a second recess in the second region of the substrate,
- wherein the buried gate structure comprises a first gate insulating layer on the first recess, a lower filling layer at a lower portion of the buried gate structure, an upper filling layer at an upper portion of the buried gate structure, and a first work function adjustment layer between the upper filling layer and the first gate insulating layer,
- wherein the recess gate structure comprises a second gate insulating layer on the second recess, a second work function adjustment layer on the second gate insulating layer, and a filling layer on the second work function adjustment layer,
- wherein the first work function adjustment layer comprises a material the same as a material included in the second work function adjustment layer,
- wherein the first work function adjustment layer comprises a portion between the lower filling layer and the upper filling layer,
- wherein the recess gate structure further comprises a first gate layer, a second gate layer, a third gate layer, and a gate capping layer sequentially stacked on the filling layer, and
- wherein the first gate layer, the second gate layer, the third gate layer, and the gate capping layer are not buried in the substrate.
7 more elements
A semiconductor device comprising:
- a substrate comprising a first region, a second region, and a third region;
- a buried gate structure comprising a first gate insulating layer on a first recess in the first region of the substrate and a first work function adjustment layer on the first gate insulating layer;
- a first recess gate structure comprising a second gate insulating layer on a second recess in the second region of the substrate and a second work function adjustment layer on the second gate insulating layer;
- and
- a second recess gate structure comprising a third gate insulating layer on a third recess in the third region of the substrate and a third work function adjustment layer on the third gate insulating layer,
- wherein the first work function adjustment layer and the second work function adjustment layer comprise a same material,
- wherein the first work function adjustment layer and the third work function adjustment layer comprise different materials,
- wherein the buried gate structure is a portion of a first N-type transistor,
- wherein the first recess gate structure is a portion of a second N-type transistor, and
- wherein the second recess gate structure is a portion of a P-type transistor.
7 more elements
Dependencies are inferred from the claim text.