Formation of wrap-around-contact to reduce contact resistivity
AssigneeInternational Business Machines Corporation
InventorsAdra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi
Life of this patent
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Abstract
A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.
Claims17
A field effect transistor;
- comprising:
- a gate structure on a substrate;
- a source/drain on each of opposite sides of the gate structure and on the substrate;
- a source/drain contact on each of the source/drains, wherein each of the source/drain contacts wraps around the sides of one source/drain;
- an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contacts;
- and
- a dielectric protective liner between the ILD layer and the source/drain contact, wherein a portion of each source/drain contact between an underlying source/drain and the dielectric protective liner has an outer shape that matches the outer shape on both sides of the underlying source/drain, and the dielectric protective liner is in contact with the substrate.
A field effect transistor;
- comprising:
- a gate structure on a substrate, wherein the gate structure includes a gate sidewall spacer;
- a source/drain on opposite sides of the gate structure and on the substrate;
- a source/drain contact on opposite sides of each of the source/drains, wherein each of the source/drain contacts wraps around the sides of source/drain and is in contact with the substrate on both sides of the source/drain;
- an interlayer dielectric (ILD) layer on each of the source/drain contacts;
- and
- a dielectric protective liner between the ILD layer and the source/drain contact, wherein a portion of each source/drain contact has a thickness in a range of about 2 nm to about 5 nm on both sides of the source/drain that is between an underlying source/drain and the dielectric protective liner, and wherein the dielectric protective liner is on the substrate adjacent to the source/drain contact.
A field effect transistor;
- comprising:
- a gate structure on a substrate, wherein the gate structure includes a gate sidewall spacer;
- a source/drain on opposite sides of the gate structure and on the substrate;
- a source/drain contact on opposite sides of each of the source/drains, wherein each of the source/drain contacts wraps around the sides of source/drain and is in contact with the substrate on both sides of the source/drain;
- an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contacts;
- a dielectric protective liner between the ILD layer and the source/drain contact, wherein a portion of each source/drain contact between an underlying source/drain and the dielectric protective liner has an outer shape that matches the outer shape on both sides of the underlying source/drain, and wherein the dielectric protective liner is in contact with the substrate adjacent to the source/drain contact;
- and
- a stack of channel layers between the source/drains, wherein each of the source/drains is in physical and electrical contact with the stack of channel layers.
Dependencies are inferred from the claim text.