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US 10,896,957 B2Granted
Semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsNamkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
Life of this patent
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Abstract
A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
Claims18
A semiconductor device, comprising:
- first, second, third, and fourth fin patterns sequentially disposed in a first direction on a substrate;
- at least one gate electrode intersecting the first, second, third, and fourth fin patterns;
- first, second, third, and fourth source/drain regions on upper surfaces of the first, second, third, and fourth fin patterns, respectively, the second and third source/drain regions being in contact with each other to define a merged source/drain region;
- a blocking layer on an outer sidewall of the second fin pattern opposing an inner sidewall of the second fin pattern facing the third fin pattern, the blocking layer extending above the upper surface of the second fin pattern and being in direct contact with an outer side surface of the second source/drain region opposing an inner side surface of the second source/drain region facing the third source/drain region;
- and
- spacers on the inner sidewall of the second fin pattern and both sidewalls each of the first, third, and fourth fin patterns, the spacers extending to a same height level as the first, second, third, and fourth fin patterns or lower and having a height lower than a height of the blocking layer,
- wherein the merged source/drain region has an asymmetric shape based on a center of the merged source/drain region in the first direction, and
- upper surfaces of the second and third source/drain regions are substantially flat.
5 more elements
A semiconductor device, comprising:
- first and second fin patterns sequentially disposed in a first direction on a substrate;
- third and fourth fin patterns on the substrate, the first and second fin patterns being between the third and fourth fin patterns;
- at least one gate electrode intersecting the first and second fin patterns;
- first and second source/drain regions on upper surfaces of the first and second fin patterns, respectively, the first and second source/drain regions being in contact with each other to define a merged source/drain region;
- third and fourth source/drain regions on upper surfaces of the third and fourth fin patterns, respectively, the merged source/drain region being between the third and fourth source/drain regions and spaced apart from each of the third and fourth source/drain regions;
- a blocking layer on a first sidewall of the first fin pattern opposing a second sidewall of the first fin pattern facing the second fin pattern, the blocking layer extending above the upper surface of the first fin pattern and being in direct contact with a first side surface of the first source/drain region opposing a second side surface of the first source/drain region facing the second source/drain region;
- and
- spacers on the second sidewall of the first fin pattern and both sidewalls of the second fin pattern, the spacers extending to a same height level as the first and second fin patterns or lower and having a height lower than a height of the blocking layer,
- wherein the first source/drain region has a maximum width smaller than a maximum width of the second source/drain region in the first direction, and the merged source/drain region has an asymmetric shape based on a center of the merged source/drain region in the first direction, and
- wherein upper surfaces of the first and second source/drain regions are substantially flat, and each of the third and fourth source/drain regions has a vertex on an upper surface.
7 more elements
A semiconductor device, comprising:
- first and second fin patterns extending in a first direction on a substrate;
- at least one gate electrode intersecting the first and second fin patterns and extending in a second direction;
- first and second source/drain regions on upper surfaces of the first and second fin patterns, respectively, the first and second source/drain regions being in contact with each other to define a merged source/drain region;
- a blocking layer on a first sidewall of the first fin pattern opposing a second sidewall of the first fin pattern facing the second fin pattern, the blocking layer extending above the upper surface of the first fin pattern and being in direct contact with a first side surface of the first source/drain region opposing a second side surface of the first source/drain region facing the second source/drain region;
- and
- spacers on the second sidewall of the first fin pattern and both sidewalls of the second fin pattern, the spacers extending to a same height level as the first and second fin patterns or lower and having a height lower than a height of the blocking layer,
- wherein the first side surface of the first source/drain region includes a first side being flush against the blocking layer and a second side extending upward directly from an upper end of the first side in a direction oriented toward an extension of a central vertical axis of the first fin pattern to form a vertex between the first side and the second side, and
- an upper end of the blocking layer is at substantially a same height level as a position of the vertex at which the first source/drain region has a maximum width in the second direction.
5 more elements
Dependencies are inferred from the claim text.