Field effect transistor with reduced contact resistance

A field effect transistor (FET) comprising:

• a semiconductor portion of which a first part forms a channel of the FET;
• a gate which at least partly surrounds the first part of the semiconductor portion;
• internal dielectric spacers arranged around second parts of the semiconductor portion between which the first part of the semiconductor portion is arranged and which form extension regions of the FET;
• electrically conductive portions in contact with third parts of the semiconductor portion, forming part of source and drain regions of the FET, at least partly surrounding the third parts of the semiconductor portion, with each of the second parts of the semiconductor portion being arranged between the first part of the semiconductor portion and one of the third parts of the semiconductor portion;
• doped portions in a surface of the second parts between internal dielectric spacers and undoped portions of the second parts;
• doped extremities of the third parts between the electrically conductive portions and undoped portions of the third parts;
• and
• external dielectric spacers between which the gate is arranged and disposed on an assembly including the second and third parts of the semiconductor portion, the internal dielectric spacers, and the parts of the electrically conductive portions in contact with doped surfaces of the third parts of the semiconductor portion,
• wherein the first part, the second parts, the extremities, and the third parts are all formed from a same material that forms the semiconductor portion,
• wherein the semiconductor portion is suspended above a substrate,
• wherein a part of each of the external dielectric spacers abuts an internal dielectric spacer of the internal dielectric spacers such that a surface of the part of each of the external dielectric spacers and a surface of the internal dielectric spacer abut each other, and the surface of the part and the surface of the internal dielectric spacer both intersect an imaginary line extending from the substrate in a direction normal to the substrate, and
• wherein the extremities are surfaces of the semiconductor portion, which are perpendicular to a direction along which the semiconductor portion extends, perpendicular to the surface of the part and the surface of the internal dielectric spacer that abut each other, and parallel to the imaginary line, found at ends of the third parts.