Semiconductor device including a functional layer and a method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKangmook Lim, Sang Su Kim, Woo Seok Park, Sung Gi Hur
Life of this patent
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Abstract
A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.
Claims17
A semiconductor device comprising:
- a substrate;
- an active region disposed on the substrate and extending in a first direction;
- a device isolation layer adjacent to the active region;
- a gate structure disposed on the active region, the gate structure extending in a second direction crossing the first direction and covering a portion of the device isolation layer;
- a gate separation pattern contacting an end of the gate structure;
- and
- an impurity region disposed below the gate separation pattern and on the device isolation layer,
- wherein the device isolation layer surrounds a bottom surface and at least two side surfaces of the impurity region in a cross-sectional view, and a top surface of the impurity region is in contact with the gate separation pattern.
A semiconductor device comprising:
- a substrate;
- a plurality of active regions disposed on the substrate;
- a device isolation layer adjacent to the plurality of active regions;
- a plurality of gate structures at least partially overlapping the plurality of active regions and contacting the device isolation layer;
- a gate separation pattern disposed between adjacent gate structures of the plurality of gate structures and on the device isolation layer;
- and
- a low etch-rate region disposed between the gate separation pattern and the device isolation layer,
- wherein the low etch-rate region has a lower etch-rate than the device isolation layer, and
- wherein the device isolation layer surrounds a bottom surface and at least two side surfaces of the low etch-rate region in a cross-sectional view, and a top surface of the etch-rate region is in contact with the gate separation pattern.
Dependencies are inferred from the claim text.