US 10,896,918 B1 · Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other.

Claims17

Dependent claims

A semiconductor memory device comprising:

a stack with a cell area and a connection area disposed over a substrate;
a plurality of channel structures passing through the stack in the cell area;
and
a plurality of slits,
the stack comprising:
a plurality of first dielectric layers;
a plurality of electrode layers alternately stacked with the plurality of first dielectric layers in the cell area and in a periphery of the connection area;
and
a plurality of second dielectric layers alternately stacked with the plurality of first dielectric layers in a center of the connection area,
wherein a distance between the slits in the connection area is greater than a distance between the slits in the cell area, and
wherein, at an intersection of the periphery and the center of the connection area, one of the plurality of the electrode layers and one of the plurality of the second dielectric layers are in contact with each other.

8 more elements

A semiconductor memory device comprising:

a memory structure disposed over a first substrate;
and
a logic structure disposed over a second substrate,
the memory structure comprising:
a stack with a cell area and a connection area disposed over the first substrate;
a plurality of channel structures passing through the stack in the cell area;
and
a plurality of slits,
the stack comprising:
a plurality of first dielectric layers;
a plurality of electrode layers alternately stacked with the plurality of first dielectric layers in the cell area and in a periphery of the connection area;
and
a plurality of second dielectric layers alternately stacked with the plurality of first dielectric layers in a center of the connection area,
wherein a distance between the slits in the connection area is greater than a distance between the slits in the cell area, and
wherein, at an intersection of the periphery and the center of the connection area, one of the plurality of the electrode layers and one of the plurality of the second dielectric layers are in contact with each other.

12 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and manufacturing method thereof

Life of this patent

Semiconductor memory device and manufacturing method thereof

Life of this patent

Abstract

Claims17