Semiconductor device

A 3-dimensional semiconductor memory device comprising:

• a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction;
• a stacked memory cell array formed on the semiconductor substrate;
• a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction;
• an upper insulating layer formed above the plurality of memory cell structures and separation lines;
• and
• a passivation layer formed above the upper insulating layer, wherein:
• the passivation layer includes a plurality of first regions having a first vertical thickness,
• a plurality of gap regions in the passivation layer are formed between the plurality of first regions,
• the plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines,
• the plurality of gap regions comprise a plurality of second regions of the passivation layer having a second vertical thickness, and
• a ratio of the first vertical thickness to the second vertical thickness is between 5:3 and 5:4.

A vertical NAND (VNAND) semiconductor device comprising:

• a semiconductor substrate;
• a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack, and forming a plurality of gate stack structures extending in a first horizontal direction and separated from each other in a second horizontal direction perpendicular to the first direction;
• a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings;
• a plurality of separation areas extending in the first horizontal direction and arranged in the second horizontal direction between the plurality of gate stack structures to separate the gate stack structures from each other;
• an upper insulating layer formed above the plurality of gate electrode layers;
• and
• a passivation layer formed above the upper insulating layer,
• wherein:
• the passivation layer includes a plurality of first regions having a first vertical thickness,
• a plurality of gap regions in the passivation layer are formed between the plurality of first regions,
• the plurality of first regions vertically overlap the plurality of gate stack structures, and the plurality of gap regions vertically overlap the plurality of separation areas, and
• a ratio of the first vertical thickness to a thickness of the semiconductor device between a top surface of the semiconductor substrate and a bottom surface of the passivation layer is between 1:25 to 1:6.